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DC Field | Value | Language |
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dc.citation.conferencePlace | JA | - |
dc.citation.conferencePlace | Yokohama | - |
dc.citation.title | IEEE Symposium on Low-Power and High-Speed Chips | - |
dc.contributor.author | Kim, Gyeonghoon | - |
dc.contributor.author | Park, Seongwook | - |
dc.contributor.author | Lee, Kyuho | - |
dc.contributor.author | Kim, Youchang | - |
dc.contributor.author | Hong, Injoon | - |
dc.contributor.author | Bong, Kyeongryeol | - |
dc.contributor.author | Shin, Dongjoon | - |
dc.contributor.author | Choi, Sungpill | - |
dc.contributor.author | Park, Junyoung | - |
dc.contributor.author | Yoo, Hoi-Jun | - |
dc.date.accessioned | 2023-12-20T00:08:12Z | - |
dc.date.available | 2023-12-20T00:08:12Z | - |
dc.date.created | 2018-08-07 | - |
dc.date.issued | 2014-04-14 | - |
dc.description.abstract | A 36 Heterogeneous multicore processor is proposed to accelerate recognition-based markerless augmented reality. To enable a real-time operation of the proposed augmented reality, task-level pipelined multicore architecture with DLP/TLP optimized SIMD processing elements is implemented. In addition, the multicore employs a congestion-aware network-on-chip scheduler for 2D-mesh network-on-chip to support massive internal data transaction caused by task-level pipeline. As a result, it achieves 1.22TOPS peak performance and 1.57TOPS/W energy-efficiency, which are 88% and 76% improvement over a state-of-the-art augmented reality processor, for 30fps 720p test input video. | - |
dc.identifier.bibliographicCitation | IEEE Symposium on Low-Power and High-Speed Chips | - |
dc.identifier.doi | 10.1109/CoolChips.2014.6842959 | - |
dc.identifier.scopusid | 2-s2.0-84904688611 | - |
dc.identifier.uri | https://scholarworks.unist.ac.kr/handle/201301/37386 | - |
dc.identifier.url | https://ieeexplore.ieee.org/document/6842959/ | - |
dc.language | 영어 | - |
dc.publisher | 17th IEEE Symposium on Low-Power and High-Speed Chips, COOL Chips 2014 | - |
dc.title | A task-level pipelined many-SIMD augmented reality processor with congestion-aware network-on-chip scheduler | - |
dc.type | Conference Paper | - |
dc.date.conferenceDate | 2014-04-14 | - |
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