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- Lee, Kyuho Jason
- Intelligent Systems Lab.
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A task-level pipelined many-SIMD augmented reality processor with congestion-aware network-on-chip scheduler
- Author(s)
- Kim, Gyeonghoon, Park, Seongwook, Lee, Kyuho, Kim, Youchang, Hong, Injoon, Bong, Kyeongryeol, Shin, Dongjoon, Choi, Sungpill, Park, Junyoung, Yoo, Hoi-Jun
- Issued Date
- 2014-04-14
- Citation
- IEEE Symposium on Low-Power and High-Speed Chips
- Abstract
- A 36 Heterogeneous multicore processor is proposed to accelerate recognition-based markerless augmented reality. To enable a real-time operation of the proposed augmented reality, task-level pipelined multicore architecture with DLP/TLP optimized SIMD processing elements is implemented. In addition, the multicore employs a congestion-aware network-on-chip scheduler for 2D-mesh network-on-chip to support massive internal data transaction caused by task-level pipeline. As a result, it achieves 1.22TOPS peak performance and 1.57TOPS/W energy-efficiency, which are 88% and 76% improvement over a state-of-the-art augmented reality processor, for 30fps 720p test input video.
- Publisher
- 17th IEEE Symposium on Low-Power and High-Speed Chips, COOL Chips 2014
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