European Solid-State Circuits Conference, pp.100 - 103
Abstract
An Intelligent Task Scheduler (ITS) together with Congestion-avoiding Flexible Routing (CAFeR) are proposed to minimize network congestion of network-on-chip (NoC), so as to improve the throughput of multi-core system for fast and accurate object recognition. The ITS predicts the communication pattern of next frame and intelligently assigns tasks to consumer cores. It also adaptively controls buffer threshold of each link in NoC to support CAFeR to enhance packet transaction throughput, which enables packets to communicate with less congestion. Thanks to the proposed ITS with 91.4% of prediction accuracy and CAFeR, the overall latency is reduced by 50.2%.
Publisher
41st European Solid-State Circuits Conference, ESSCIRC 2015