dc.citation.conferencePlace |
JA |
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dc.citation.conferencePlace |
19th IEEE Symposium on Low-Power and High-Speed Chips, IEEE COOL Chips 2016 |
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dc.citation.title |
IEEE Symposium on Low-Power and High-Speed Chips |
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dc.contributor.author |
Lee, Kyuho |
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dc.contributor.author |
Bong, Kyeongryeol |
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dc.contributor.author |
Kim, Changhyeon |
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dc.contributor.author |
Park, Junyoung |
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dc.contributor.author |
Yoo, Hoi-Jun |
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dc.date.accessioned |
2023-12-19T21:06:26Z |
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dc.date.available |
2023-12-19T21:06:26Z |
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dc.date.created |
2018-08-07 |
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dc.date.issued |
2016-04-20 |
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dc.description.abstract |
A heterogeneous multicore processor is proposed to accelerate advanced driver assistance system (ADAS). To enable a real-time operation of ADAS functions with 720p stereo video stream, multiple granualrity parallel SIMD/MIMD architecture is proposed with precise visual attention and high throughput network-on-chip to reduce computation cost and network congestion, respectively. In addition, it employs a data resource management processor to control workload-prediction dynamic voltage and frequency scaling to reduce power consumption. As a result, the proposed SoC ahcieves 862GOPS/W energy efficiency and 31.4GOPS/mm2 area efficiency, which are 53% and 75% improvement over the state-of-the-art ADAS processor, respectively. |
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dc.identifier.bibliographicCitation |
IEEE Symposium on Low-Power and High-Speed Chips |
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dc.identifier.doi |
10.1109/CoolChips.2016.7503672 |
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dc.identifier.scopusid |
2-s2.0-84982854127 |
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dc.identifier.uri |
https://scholarworks.unist.ac.kr/handle/201301/37355 |
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dc.identifier.url |
https://ieeexplore.ieee.org/document/7503672/ |
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dc.language |
영어 |
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dc.publisher |
19th IEEE Symposium on Low-Power and High-Speed Chips, IEEE COOL Chips 2016 |
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dc.title |
An energy-efficient parallel multi-core ADAS processor with robust visual attention and workload-prediction DVFS for real-time HD stereo stream |
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dc.type |
Conference Paper |
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dc.date.conferenceDate |
2016-04-20 |
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