dc.citation.conferencePlace |
US |
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dc.citation.conferencePlace |
Hilton Hawaiian VillageHonolulu |
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dc.citation.endPage |
157 |
- |
dc.citation.startPage |
156 |
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dc.citation.title |
21st IEEE Silicon Nanoelectronics Workshop (SNW 2016) |
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dc.contributor.author |
Jang, Esan |
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dc.contributor.author |
Shin, Sunhae |
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dc.contributor.author |
Jung, Jae Won |
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dc.contributor.author |
Jung, Yu Jung |
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dc.contributor.author |
Kim, Kyung Rok |
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dc.date.accessioned |
2023-12-19T20:37:42Z |
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dc.date.available |
2023-12-19T20:37:42Z |
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dc.date.created |
2016-11-28 |
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dc.date.issued |
2016-06-12 |
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dc.description.abstract |
We propose a new optimized design strategy by considering the correlated effects of high-κ gate oxide and spacer dielectric on GIDL and DIBL in nanoscale MOSFET. By investigating the transition of GIDL mechanism from vertical to lateral in 32 nm nMOS with abrupt and high drain extension doping, the lateral GIDL is suppressed by 10-4 with high-κ spacer (e.g. TiO2). DIBL is also suppressed below 100 mV/V by taking relatively lower-κ gate oxide (e.g. HfO2) than high-κ spacer. |
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dc.identifier.bibliographicCitation |
21st IEEE Silicon Nanoelectronics Workshop (SNW 2016), pp.156 - 157 |
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dc.identifier.doi |
10.1109/SNW.2016.7578030 |
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dc.identifier.isbn |
978-150900726-4 |
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dc.identifier.scopusid |
2-s2.0-84994728970 |
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dc.identifier.uri |
https://scholarworks.unist.ac.kr/handle/201301/37343 |
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dc.identifier.url |
http://ieeexplore.ieee.org/document/7578030/ |
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dc.language |
영어 |
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dc.publisher |
IEEE |
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dc.title |
Device optimization on gate oxide and spacer dielectric permittivity for 'well-tempered' nanoscale MOSFET |
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dc.type |
Conference Paper |
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dc.date.conferenceDate |
2016-06-12 |
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