HAPT: Hardware-accelerated persistent transactions

Abstract

Persistent memory (PM) is rapidly emerging as a promising technology with its useful properties such as durability, DRAM-like performance, and byte addressability. However, programming PM is challenging because programmers need to manually orchestrate all the persists with the cache flush operations and persist barriers to ensure the correct execution of their code. To improve the programmability of PM, prior work has extensively investigated the hardware and software techniques for persistent transactions. While insightful, the existing techniques either significantly increase hardware complexity due to the intrusive modifications of the processors, caches, and memory hierarchy or incur significant performance overheads due to the transactional activities solely performed in software. To bridge this gap, this work proposes a hybrid system called HAPT, hardware-accelerated persistent transactions. HAPT accelerates the address translation process for aliased memory operations based on the alias management unit (AMU), which is a lightweight hardware structure. HAPT performs most of the transactional activities in software, achieving low hardware complexity and high flexibility. Our quantitative evaluation demonstrates that HAPT significantly outperforms the state-of-the-art software system for persistent transactions and continues to provide large performance gains even when the AMU is configured with small capacity or long access latency.