dc.citation.conferencePlace |
JA |
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dc.citation.conferencePlace |
Rihga Royal HotelKyoto |
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dc.citation.endPage |
C159 |
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dc.citation.startPage |
C158 |
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dc.citation.title |
IEEE Symposium on VLSI Circuits |
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dc.contributor.author |
Lee, Jinsu |
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dc.contributor.author |
Shin, Dongjoo |
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dc.contributor.author |
Lee, Kyuho |
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dc.contributor.author |
Yoo, Hoi-Jun |
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dc.date.accessioned |
2023-12-19T18:41:34Z |
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dc.date.available |
2023-12-19T18:41:34Z |
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dc.date.created |
2018-08-07 |
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dc.date.issued |
2017-06-05 |
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dc.description.abstract |
An energy-efficient and high-speed stereo matching processor is proposed for smart mobile devices with proposed stereo SRAM (S-SRAM) and independent regional integral cost (IRIC). Cost generation unit (CGU) with the proposed S-SRAM reduces 63.2% of CGU power consumption. The proposed IRIC enables cost aggregation unit (CAU) to obtain 6.4× of speed and 12.3% of the power reduction of CAU with pipelined integral cost generator (PICG). The proposed stereo matching processor, implemented in 65nm CMOS process, achieves 82fps and 31.2pJ/disparity-pixel energy efficiency at 30fps. Its energy efficiency is improved by 77.6% compared to the state-of-the-art. |
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dc.identifier.bibliographicCitation |
IEEE Symposium on VLSI Circuits, pp.C158 - C159 |
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dc.identifier.doi |
10.23919/VLSIC.2017.8008464 |
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dc.identifier.scopusid |
2-s2.0-85034035069 |
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dc.identifier.uri |
https://scholarworks.unist.ac.kr/handle/201301/37295 |
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dc.identifier.url |
https://ieeexplore.ieee.org/document/8008464/ |
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dc.language |
영어 |
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dc.publisher |
31st Symposium on VLSI Circuits, VLSI Circuits 2017 |
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dc.title |
A 31.2pJ/disparity· pixel stereo matching processor with stereo SRAM for mobile UI application |
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dc.type |
Conference Paper |
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dc.date.conferenceDate |
2017-06-05 |
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