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Logic-in-Memory Technology Mapping Framework for Memristor Crossbar with Maximized Parallelism

Kim, Ik-Kyum , Park, Heechun

Conference Paper Issue Date2024-01-24 View16
Minimum Implant Area-Aware Threshold Voltage Refinement in Pre-Placement

Jeong, Eunsol , Park, Heechun , Kim, Taewhan

Conference Paper Issue Date2021-08-09 View10
Pseudo-3D Approaches for Commercial-Grade RTL-to-GDS Tool Flow Targeting Monolithic 3D ICs

Park, Heechun , Ku, Bonwoong , Lim, Sung-kyu

Conference Paper Issue Date2020-09-20 View17
Pseudo-3D Physical Design Flow for Monolithic 3D ICs: Comparisons and Enhancements File

Park , Heechun , Ku, Bon Woong , Chang, Kyungwook , Shim, Da Eun , Lim, Sung Kyu

Article Issue Date2021-09 View23
RTL-to-GDS Design Tools for Monolithic 3D ICs Built with Carbon Nanotube Transistors and Resistive Memory

Kim, Jinwoo , Park, Heechun , Lim, Sung Kyu

Conference Paper Issue Date2020-03-16 View21
RTL-to-GDS Tool Flow and Design-for-Test Solutions for Monolithic 3D ICs

Park, Heechun , Chang, Kyungwook , Lim, Sung Kyu

Conference Paper Issue Date2019-06-02 View22
Safety Verification of AMS Circuits with Piecewise-Linear System Reachability Analysis

Kim, Seyoung , Park , Heechun , Kim, Jaeha

Conference Paper Issue Date2021-10-06 View17
Speeding-up neuromorphic computation for neural networks: Structure optimization approach File

Park , Heechun , Kim, Taewhan

Article Issue Date2022-01 View17
Structure Optimizations of Neuromorphic Computing Architectures for Deep Neural Networks

Park, Heechun , Kim, Taewhan

Conference Paper Issue Date2018-03-19 View17
Synthesis of TSV Fault-Tolerant 3-D Clock Trees File

Park, Heechun , Kim, Taewhan

Article Issue Date2015-02 View20
Synthesizing Asynchronous Circuits Toward Practical Use File

Park, Heechun , Kim, Taewhan

Conference Paper Issue Date2016-07-11 View17
Tightly Linking 3D via Allocation towards Routing Optimization for Monolithic 3D ICs

Kim, Suwan , Chung, Sehyeon , Park , Heechun

Conference Paper Issue Date2022-08-01 View13
Timing-Aware Tier Partitioning for 3D ICs With Critical Path Consideration

Park, Sojung , Park , Heechun

Conference Paper Issue Date2024-01-28 View18
Timing-Aware Tier Partitioning for 3D ICs With Critical Path Consideration

Park, Sojung , Park, Heechun

Conference Paper Issue Date2024-01-24 View14
Unsupervised Learning-Based Legalization with Graph Neural Network

Lim, Dho Ui , Park, Heechun

Conference Paper Issue Date2024-01-24 View18
비동기식 회로 설계 구조에 대한 전력 및 면적 비교

Park, Heechun , Kim, Taewhan

Conference Paper Issue Date2015-11-27 View14
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