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dc.citation.endPage 12 -
dc.citation.number 1 -
dc.citation.startPage 9 -
dc.citation.title IEEE COMPUTER ARCHITECTURE LETTERS -
dc.citation.volume 9 -
dc.contributor.author Park, Seon-yeong -
dc.contributor.author Seo, Euiseong -
dc.contributor.author Shin, Ji-Yong -
dc.contributor.author Maeng, Seungryoul -
dc.contributor.author Lee, Joonwon -
dc.date.accessioned 2023-12-22T07:36:18Z -
dc.date.available 2023-12-22T07:36:18Z -
dc.date.created 2013-06-18 -
dc.date.issued 2010-01 -
dc.description.abstract For the last few years, the major driving force behind the rapid performance improvement of SSDs has been the increment of parallel bus channels between a flash controller and flash memory packages inside the solid-state drives (SSDs). However, there are other internal parallelisms inside SSDs yet to be explored. In order to improve performance further by utilizing the parallelism, this paper suggests request rescheduling and dynamic write request mapping. Simulation results with real workloads have shown that the suggested schemes improve the performance of the SSDs by up to 15% without any additional hardware support. -
dc.identifier.bibliographicCitation IEEE COMPUTER ARCHITECTURE LETTERS, v.9, no.1, pp.9 - 12 -
dc.identifier.doi 10.1109/L-CA.2010.3 -
dc.identifier.issn 1556-6056 -
dc.identifier.scopusid 2-s2.0-77953292925 -
dc.identifier.uri https://scholarworks.unist.ac.kr/handle/201301/3646 -
dc.identifier.url http://www.scopus.com/inward/record.url?partnerID=HzOxMe3b&scp=77953292925 -
dc.identifier.wosid 000288081600003 -
dc.language 영어 -
dc.publisher IEEE COMPUTER SOC -
dc.title Exploiting Internal Parallelism of Flash-based SSDs -
dc.type Article -
dc.description.isOpenAccess FALSE -
dc.relation.journalWebOfScienceCategory Computer Science, Hardware & Architecture -
dc.relation.journalResearchArea Computer Science -
dc.description.journalRegisteredClass scie -
dc.description.journalRegisteredClass scopus -

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