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DC Field | Value | Language |
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dc.citation.conferencePlace | US | - |
dc.citation.conferencePlace | Fort Worth, TX | - |
dc.citation.endPage | 108 | - |
dc.citation.startPage | 105 | - |
dc.citation.title | IEEE MTT-S International Microwave Symposium | - |
dc.contributor.author | Bien, Franklin | - |
dc.contributor.author | Hur, Y | - |
dc.contributor.author | Chandramouli, S | - |
dc.contributor.author | Kim, H | - |
dc.contributor.author | Kumar, Y | - |
dc.contributor.author | Chun, C | - |
dc.contributor.author | Gebara, E | - |
dc.contributor.author | Laskar, J | - |
dc.contributor.author | Maeng, M | - |
dc.date.accessioned | 2023-12-20T05:39:51Z | - |
dc.date.available | 2023-12-20T05:39:51Z | - |
dc.date.created | 2014-12-23 | - |
dc.date.issued | 2004-06-06 | - |
dc.description.abstract | In this paper, we present a 20 Gbps throughput PAM-4 analog feed forward equalizer with a newly proposed multiplier cell. The conventional Gilbert-cell multiplier is modified to achieve enough voltage headroom for 0.18/spl mu/m standard CMOS process while maintaining high-speed characteristics. Pulse amplitude modulation (PAM)-4 is adopted to increase the overall data throughput over bandwidth limited channel. For the tap delay line implementation, a passive L-C ladder topology is used, which enables fractional symbol tap spacing while maintaining the bandwidth required for 20 Gbps PAM-4 signal. The overall architecture is implemented using 0.18 /spl mu/m, standard CMOS process with 1.8V supply voltage. The 20 Gbps PAM-4 signal is received through the backplane channel, and the signal impairment is successfully compensated through the fabricated FFE. | - |
dc.identifier.bibliographicCitation | IEEE MTT-S International Microwave Symposium, pp.105 - 108 | - |
dc.identifier.issn | 0149-645X | - |
dc.identifier.scopusid | 2-s2.0-4444237551 | - |
dc.identifier.uri | https://scholarworks.unist.ac.kr/handle/201301/35833 | - |
dc.identifier.url | https://ieeexplore.ieee.org/document/1335813 | - |
dc.language | 영어 | - |
dc.publisher | IEEE Microwave Theory and Tech | - |
dc.title | A 0.18μm CMOS equalizer with an improved multiplier for 4-PAM/20Gbps throughput over 20 inch FR-4 backplane channels | - |
dc.type | Conference Paper | - |
dc.date.conferenceDate | 2004-06-06 | - |
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