dc.citation.conferencePlace |
KO |
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dc.citation.title |
2016 IEEE International Conference on Consumer Electronics-Asia, ICCE-Asia 2016 |
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dc.contributor.author |
Lee, Jaemin |
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dc.contributor.author |
Kim, Sunmean |
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dc.contributor.author |
Kim, Youngmin |
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dc.contributor.author |
Kang, Seokhyeong |
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dc.date.accessioned |
2023-12-19T20:06:09Z |
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dc.date.available |
2023-12-19T20:06:09Z |
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dc.date.created |
2017-02-17 |
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dc.date.issued |
2016-10-26 |
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dc.description.abstract |
Recently, supply voltage has been reduced for low power applications, and near threshold computing (NTC) is considered as a promising solution for optimal energy efficiency. However, NTC suffers a significant performance degradation, which is prone to timing errors. Thus, in order to improve the reliability of NTC operations, error-resilient techniques are indispensable, though they cause area and power overheads. In this paper, we propose a design methodology which provides an optimal implementation of error-resilient circuits. A modified Quine-McCluskey (Q-M) algorithm is exploited to earn the minimum set of error-resilient circuits without any loss of detection ability. From the proposed design flow, benchmark results show that optimal design reduces up to 72% of required flip-flops to be changed to error-resilient circuits without compromising an error detection ability. |
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dc.identifier.bibliographicCitation |
2016 IEEE International Conference on Consumer Electronics-Asia, ICCE-Asia 2016 |
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dc.identifier.doi |
10.1109/ICCE-Asia.2016.7804807 |
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dc.identifier.scopusid |
2-s2.0-85011051982 |
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dc.identifier.uri |
https://scholarworks.unist.ac.kr/handle/201301/35359 |
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dc.identifier.url |
http://ieeexplore.ieee.org/document/7804807 |
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dc.language |
영어 |
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dc.publisher |
IEEE |
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dc.title |
A novel design methodology for error-resilient circuits in near-Threshold computing |
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dc.type |
Conference Paper |
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dc.date.conferenceDate |
2016-10-26 |
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