dc.citation.conferencePlace |
US |
- |
dc.citation.endPage |
16 |
- |
dc.citation.startPage |
13 |
- |
dc.citation.title |
The 17th IEEE International Conference on Nanotechnology (IEEE NANO 2017) |
- |
dc.contributor.author |
Shin, Sunhae |
- |
dc.contributor.author |
Jeong, Jae Won |
- |
dc.contributor.author |
Jang, Esan |
- |
dc.contributor.author |
Kim, Kyung Rok |
- |
dc.date.accessioned |
2023-12-19T18:37:17Z |
- |
dc.date.available |
2023-12-19T18:37:17Z |
- |
dc.date.created |
2017-10-19 |
- |
dc.date.issued |
2017-07-26 |
- |
dc.description.abstract |
We demonstrate ternary CMOS (T-CMOS)-based standard ternary inverter (STI) for compact and powerscalable multi-valued logic (MVL) circuits. The distinguished mechanism of VG-independent junction band-to-band tunneling (BTBT) for ternary logic has been successfully obtained by CMOS process with a few pA/m level which enables STI operation with ultra-low static power consumption of 7.7 pW/m. Through the STI performance investigation with various T-CMOS structures by using TCAD simulation, advanced nanoscale bulk tri-gate (TG) ternary FinFET (TFinFET) shows highly noise-immune STI operation with a larger static noise margin (SNM) of 94% to the ideal SNM (230mV) than 86% of bulk planar T-CMOS and 75% of SOI TCMOS technology. |
- |
dc.identifier.bibliographicCitation |
The 17th IEEE International Conference on Nanotechnology (IEEE NANO 2017), pp.13 - 16 |
- |
dc.identifier.doi |
10.1109/NANO.2017.8117372 |
- |
dc.identifier.scopusid |
2-s2.0-85041180258 |
- |
dc.identifier.uri |
https://scholarworks.unist.ac.kr/handle/201301/35276 |
- |
dc.identifier.url |
http://ieeexplore.ieee.org/document/8117372/ |
- |
dc.language |
영어 |
- |
dc.publisher |
IEEE |
- |
dc.title |
Ultra-Low Standby Power and Static Noise-Immune Standard Ternary Inverter Based on Nanoscale Ternary CMOS Technology |
- |
dc.type |
Conference Paper |
- |
dc.date.conferenceDate |
2017-07-25 |
- |