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DC Field | Value | Language |
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dc.citation.conferencePlace | CN | - |
dc.citation.conferencePlace | Vancouver, BC | - |
dc.citation.endPage | 286 | - |
dc.citation.startPage | 281 | - |
dc.citation.title | Advanced Gate Stack, Source/Drain and Channel Engineering for Si-based CMOS: New Materials, Processes and Equipment, 6 - 217th ECS Meeting | - |
dc.contributor.author | Lee, Kong-Soo | - |
dc.contributor.author | Yoo, Dae-Han | - |
dc.contributor.author | Yoo, Young-Sub | - |
dc.contributor.author | Han, Jae-Jong | - |
dc.contributor.author | Kim, Seok-Sik | - |
dc.contributor.author | Jeong, Hong-Sik | - |
dc.contributor.author | Kang, Chang-Jin | - |
dc.contributor.author | Moon, Joo-Tae | - |
dc.contributor.author | Park, Hyunho | - |
dc.contributor.author | Jeong, Hanwook | - |
dc.contributor.author | Kim, Kwang-Ryul | - |
dc.contributor.author | Choi, Byoungdeog | - |
dc.date.accessioned | 2023-12-20T03:38:12Z | - |
dc.date.available | 2023-12-20T03:38:12Z | - |
dc.date.created | 2019-07-11 | - |
dc.date.issued | 2010-04-26 | - |
dc.description.abstract | Vertical diodes for cross-point phase change memory were realized by selective epitaxial growth (SEG) technique using cyclic chemical vapor deposition method. H2/SiH4/Cl2 cyclic CVD system was introduced in batch-type vertical furnace equipement, replacing conventional single-wafer H2/dichlorosilane/HCl CVD system. It provided excellent capacity of 40 wafers per batch. Selectivity loss which is one of the most crucial features in SEG process for diode application was controlled with both the amount of SiH4 and Cl2 and the period of gas supply, and practical value of selectivity loss was confirmed to be less than 100 in 200-mm wafers. Structural and electrical properties of pn diodes were investigated, and cyclic SEG silicon diode showed more eligible electrical ability to current flow than that of poly-si in terms of forward current and ideality factor as well as lower reverse leakage current. | - |
dc.identifier.bibliographicCitation | Advanced Gate Stack, Source/Drain and Channel Engineering for Si-based CMOS: New Materials, Processes and Equipment, 6 - 217th ECS Meeting, pp.281 - 286 | - |
dc.identifier.doi | 10.1149/1.3375613 | - |
dc.identifier.issn | 1938-5862 | - |
dc.identifier.scopusid | 2-s2.0-78650581938 | - |
dc.identifier.uri | https://scholarworks.unist.ac.kr/handle/201301/34925 | - |
dc.identifier.url | http://ecst.ecsdl.org/content/28/1/281 | - |
dc.language | 영어 | - |
dc.publisher | Electronics and Photonics | - |
dc.title | Selective epitaxial growth of silicon layer using batch-type equipment for vertical diode application for next generation memories | - |
dc.type | Conference Paper | - |
dc.date.conferenceDate | 2010-04-26 | - |
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