File Download

There are no files associated with this item.

  • Find it @ UNIST can give you direct access to the published full text of this article. (UNISTARs only)

Views & Downloads

Detailed Information

Cited time in webofscience Cited time in scopus
Metadata Downloads

Full metadata record

DC Field Value Language
dc.citation.conferencePlace US -
dc.citation.conferencePlace San Francisco -
dc.citation.endPage 195 -
dc.citation.startPage 194 -
dc.citation.title IEEE International Solid-State Circuits Conference - Choi, Seojin - Yoo, Seyeon - Choi, Jaehyouk - 2023-12-19T21:09:21Z - 2023-12-19T21:09:21Z - 2016-05-03 - 2016-02-02 -
dc.description.abstract An injection-locked clock multiplier (ILCM) is considered to be a promising solution that can generate low-jitter, high-frequency clocks, using a limited budget in terms of silicon area and power consumption. However, an ILCM has a critical problem in that its jitter performance is sensitive to process, voltage, and temperature (PVT) variations. Thus, in general, an ILCM must be equipped with a dedicated PVT-calibrator to mitigate the sensitivity of its performance to PVT variations. One of the most general calibration methods is to use a phase-locked loop (PLL). This method can correct static frequency deviations of a voltage-controlled oscillator (VCO) due to process variations, but it cannot prevent real-time frequency drifts due to temperature or voltage variations [1]. Recently, many efforts have been made to develop new PVT-calibrators, capable of continuous frequency tracking [1-6]. In [1-3], frequency drifts were monitored by a replica-VCO or a delay-locked loop (DLL) that used the same delay cells as the main VCO. However, in these architectures, each calibrator must spend the same amount of the power as the VCO. In addition, mismatches between delay cells limit the calibrating precision or demand an additional calibrating step. References [4-6] presented frequency-tracking loops (FTLs) based on various methods to detect the phase shifts of VCO outputs when reference-pulses are injected. Reference [4] used a time-to-digital converter (TDC) to detect the phase shifts, but it had large power consumption and silicon area due to the many digital circuits. Although the FTL of [5] used a timing-adjusted phase detector (PD), it could suffer from large in-band noise or spurs since the switches of the charge pump (CP) must be on for a considerable duration in every period. In [6], a pulse-gating technique that periodically skipped the injection was presented, but it could generate fractional spurs. -
dc.identifier.bibliographicCitation IEEE International Solid-State Circuits Conference, pp.194 - 195 -
dc.identifier.doi 10.1109/ISSCC.2016.7417973 -
dc.identifier.issn 0193-6530 -
dc.identifier.scopusid 2-s2.0-84962808810 -
dc.identifier.uri -
dc.identifier.url -
dc.language 영어 -
dc.publisher IEEE -
dc.title 10.7 A 185fsrms-integrated-jitter and -245dB FOM PVT-robust ring-VCO-based injection-locked clock multiplier with a continuous frequency-tracking loop using a replica-delay cell and a dual-edge phase detector -
dc.type Conference Paper - 2016-01-31 -


Items in Repository are protected by copyright, with all rights reserved, unless otherwise indicated.