dc.citation.conferencePlace |
US |
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dc.citation.conferencePlace |
Hilton Hawaiian VillageHonolulu |
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dc.citation.title |
IEEE Symposium on VLSI Circuits |
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dc.contributor.author |
Lee, Yongsun |
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dc.contributor.author |
Yoon, Heein |
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dc.contributor.author |
Choi, Jaehyouk |
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dc.date.accessioned |
2023-12-19T20:37:34Z |
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dc.date.available |
2023-12-19T20:37:34Z |
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dc.date.created |
2016-08-05 |
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dc.date.issued |
2016-06-15 |
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dc.description.abstract |
This paper presents a low-reference-spur and low-jitter injection-locked clock multiplier (ILCM). To secure these performances over PVT-variations, we propose the use of a voltage-domain period-calibrating loop (VDPCL) in the ILCM that monitors the intrinsic period of the VCO and stores this information as the charges in a capacitor. By evaluating the voltage of the capacitor, it is possible to correct the free-running frequency of the VCO. By iteratively accumulating charges, the precision of the calibration can be increased. The measured reference spur and RMS jitter were -59 dBc and 450 fs, respectively, and their degradations over the PVT were less than 1.5 dB and 50 fs, respectively. |
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dc.identifier.bibliographicCitation |
IEEE Symposium on VLSI Circuits |
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dc.identifier.doi |
10.1109/VLSIC.2016.7573550 |
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dc.identifier.scopusid |
2-s2.0-84990943383 |
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dc.identifier.uri |
https://scholarworks.unist.ac.kr/handle/201301/32798 |
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dc.identifier.url |
http://ieeexplore.ieee.org/abstract/document/7573550/ |
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dc.language |
영어 |
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dc.publisher |
IEEE |
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dc.title |
A PVT-Robust Low Reference Spur Injection-Locked Clock Multiplier Using a Voltage-Domain Period-Calibrating Loop |
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dc.type |
Conference Paper |
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dc.date.conferenceDate |
2016-06-15 |
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