dc.citation.conferencePlace |
US |
- |
dc.citation.conferencePlace |
San Francisco |
- |
dc.citation.endPage |
199 |
- |
dc.citation.startPage |
198 |
- |
dc.citation.title |
2005 IEEE International Solid-State Circuits Conference, ISSCC |
- |
dc.contributor.author |
Kim, Seong-Jin |
- |
dc.contributor.author |
Lee, Kwang-Hyun |
- |
dc.contributor.author |
Han, Sang-Wook |
- |
dc.contributor.author |
Yoon, Euisik |
- |
dc.date.accessioned |
2023-12-20T05:37:19Z |
- |
dc.date.available |
2023-12-20T05:37:19Z |
- |
dc.date.created |
2015-07-29 |
- |
dc.date.issued |
2005-02-08 |
- |
dc.description.abstract |
A CMOS fingerprint recognition SoC with embedded column-parallel processors is optimized for 2D digital image processing. The processor employs self-configuration features for adaptive filter operations and the pixel includes a sensing block, ADC and frame memory without area penalty. The total image processing time is less than 360 ms at 10 MHz. |
- |
dc.identifier.bibliographicCitation |
2005 IEEE International Solid-State Circuits Conference, ISSCC, pp.198 - 199 |
- |
dc.identifier.scopusid |
2-s2.0-28144445340 |
- |
dc.identifier.uri |
https://scholarworks.unist.ac.kr/handle/201301/32426 |
- |
dc.language |
영어 |
- |
dc.publisher |
2005 IEEE International Solid-State Circuits Conference, ISSCC |
- |
dc.title |
A 200×160 Pixel CMOS Fingerprint Recognition SoC with Adaptable Column-Parallel Processors |
- |
dc.type |
Conference Paper |
- |
dc.date.conferenceDate |
2005-02-06 |
- |