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DC Field | Value | Language |
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dc.citation.endPage | 4732 | - |
dc.citation.number | 12 | - |
dc.citation.startPage | 4719 | - |
dc.citation.title | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS | - |
dc.citation.volume | 67 | - |
dc.contributor.author | Lee, Kyuho Jason | - |
dc.contributor.author | Lee, Jinmook | - |
dc.contributor.author | Choi, Sungpill | - |
dc.contributor.author | Yoo, Hoi-Jun | - |
dc.date.accessioned | 2023-12-21T16:40:38Z | - |
dc.date.available | 2023-12-21T16:40:38Z | - |
dc.date.created | 2020-06-21 | - |
dc.date.issued | 2020-12 | - |
dc.description.abstract | This paper provides a review of design approaches towards artificial intelligence (AI) System-on-Chip. AI algorithms have progressed over the past decades from perceptron-based neural network (NN) and neuro-fuzzy (NF) system to today's deep neural network (DNN) and neuromorphic computing. Recent DNN hardware accelerators focus on energy-efficient integration of digital circuits to realize real-time DNN operation while neuromorphic processors deploy new memory technologies with analog computation for low power consumption. However, different design approaches can be applied to such processor implementation with their pros and cons. This paper reviews from the early processor designs for NN and NF in both mixed-mode and digital implementations to the recent DNN SoC designs that we have proposed for a decade. The former content deals with NN and NF processors used as a functional building block of a machine vision SoC, while the latter concentrates on integration of the whole DNN function. We also provide a discussion on the approaches, and provide perspective on future research directions. | - |
dc.identifier.bibliographicCitation | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.67, no.12, pp.4719 - 4732 | - |
dc.identifier.doi | 10.1109/TCSI.2020.2996625 | - |
dc.identifier.issn | 1549-8328 | - |
dc.identifier.scopusid | 2-s2.0-85097331854 | - |
dc.identifier.uri | https://scholarworks.unist.ac.kr/handle/201301/32386 | - |
dc.identifier.url | https://ieeexplore.ieee.org/document/9104667 | - |
dc.identifier.wosid | 000596021000047 | - |
dc.language | 영어 | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | The Development of Silicon for AI: Different Design Approaches | - |
dc.type | Article | - |
dc.description.isOpenAccess | FALSE | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.relation.journalResearchArea | Engineering | - |
dc.type.docType | Article | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.subject.keywordAuthor | Noise measurement | - |
dc.subject.keywordAuthor | Computer architecture | - |
dc.subject.keywordAuthor | Neuromorphics | - |
dc.subject.keywordAuthor | Mixed-mode SoC | - |
dc.subject.keywordAuthor | neural network processor | - |
dc.subject.keywordAuthor | neuro-fuzzy processor | - |
dc.subject.keywordAuthor | deep learning SoC | - |
dc.subject.keywordAuthor | Program processors | - |
dc.subject.keywordAuthor | Artificial neural networks | - |
dc.subject.keywordAuthor | Hardware | - |
dc.subject.keywordPlus | INTELLIGENT INFERENCE ENGINE | - |
dc.subject.keywordPlus | NEURAL-NETWORK ACCELERATOR | - |
dc.subject.keywordPlus | ON-CHIP | - |
dc.subject.keywordPlus | RECOGNITION PROCESSOR | - |
dc.subject.keywordPlus | OBJECT RECOGNITION | - |
dc.subject.keywordPlus | IMPLEMENTATION | - |
dc.subject.keywordPlus | SYSTEMS | - |
dc.subject.keywordPlus | CIRCUIT | - |
dc.subject.keywordPlus | COMPUTATION | - |
dc.subject.keywordPlus | CLASSIFIER | - |
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