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DC Field | Value | Language |
---|---|---|
dc.citation.endPage | 1545 | - |
dc.citation.number | 4 | - |
dc.citation.startPage | 1534 | - |
dc.citation.title | IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY | - |
dc.citation.volume | 62 | - |
dc.contributor.author | Sun, Yin | - |
dc.contributor.author | Kim, Jingook | - |
dc.contributor.author | Ouyang, Muqi | - |
dc.contributor.author | Hwang, Chulsoon | - |
dc.date.accessioned | 2023-12-21T17:11:31Z | - |
dc.date.available | 2023-12-21T17:11:31Z | - |
dc.date.created | 2020-06-07 | - |
dc.date.issued | 2020-08 | - |
dc.description.abstract | In this article, an improved target impedance concept directly correlating circuit output jitter with power distribution network (PDN) R-L-C parameters is proposed. A systematic procedure to develop the target impedance curves is formulated and developed for common CMOS buffer circuits. The relationship between output jitter and PDN R-L-C parameters is analytically derived by evaluating the time domain voltage ripple to jitter transfer relationship along with the relationship between time domain voltage ripple and PDN R-L-C parameters. Given the transient integrated circuit switching current and the jitter specification, multiple target impedance curves can be defined for a specific circuit. The jitter and PDN R-L-C analytical correlations are validated through HSPICE simulation. The application of the proposed target impedance concept with jitter specification is also demonstrated via simulation. | - |
dc.identifier.bibliographicCitation | IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY, v.62, no.4, pp.1534 - 1545 | - |
dc.identifier.doi | 10.1109/TEMC.2020.2996430 | - |
dc.identifier.issn | 0018-9375 | - |
dc.identifier.scopusid | 2-s2.0-85089941189 | - |
dc.identifier.uri | https://scholarworks.unist.ac.kr/handle/201301/32317 | - |
dc.identifier.url | https://ieeexplore.ieee.org/document/9109550 | - |
dc.identifier.wosid | 000560360900062 | - |
dc.language | 영어 | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | Improved Target Impedance Concept With Jitter Specification | - |
dc.type | Article | - |
dc.description.isOpenAccess | FALSE | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic; Telecommunications | - |
dc.relation.journalResearchArea | Engineering; Telecommunications | - |
dc.type.docType | Article | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.subject.keywordAuthor | Jitter | - |
dc.subject.keywordAuthor | Impedance | - |
dc.subject.keywordAuthor | Time-domain analysis | - |
dc.subject.keywordAuthor | Switches | - |
dc.subject.keywordAuthor | Propagation delay | - |
dc.subject.keywordAuthor | Transfer functions | - |
dc.subject.keywordAuthor | Integrated circuits | - |
dc.subject.keywordAuthor | Buffer | - |
dc.subject.keywordAuthor | jitter | - |
dc.subject.keywordAuthor | jitter transfer function | - |
dc.subject.keywordAuthor | power supply induced jitter | - |
dc.subject.keywordAuthor | target impedance | - |
dc.subject.keywordPlus | POWER | - |
dc.subject.keywordPlus | DESIGN | - |
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