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- Lee, Jaiyong
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| DC Field | Value | Language |
|---|---|---|
| dc.citation.endPage | 136 | - |
| dc.citation.number | 2 | - |
| dc.citation.startPage | 135 | - |
| dc.citation.title | ELECTRONICS LETTERS | - |
| dc.citation.volume | 46 | - |
| dc.contributor.author | Hwang, S. O. | - |
| dc.contributor.author | Myung, S. | - |
| dc.contributor.author | Lee, H. | - |
| dc.contributor.author | Park, S. -I. | - |
| dc.contributor.author | Lee, Jaiyong | - |
| dc.date.accessioned | 2023-12-22T07:14:45Z | - |
| dc.date.available | 2023-12-22T07:14:45Z | - |
| dc.date.created | 2020-05-12 | - |
| dc.date.issued | 2010-01 | - |
| dc.description.abstract | A fast irregular repeat accumulator (IRA) encoder that reduces the encoder latency for generating parity bits is proposed. The transformation of the parity check matrix into the blockwise form and the usage of the partial parallel process bring a reduction of the number of system clocks for the IRA codes encoding. | - |
| dc.identifier.bibliographicCitation | ELECTRONICS LETTERS, v.46, no.2, pp.135 - 136 | - |
| dc.identifier.doi | 10.1049/el.2010.2896 | - |
| dc.identifier.issn | 0013-5194 | - |
| dc.identifier.scopusid | 2-s2.0-77949963123 | - |
| dc.identifier.uri | https://scholarworks.unist.ac.kr/handle/201301/32133 | - |
| dc.identifier.url | https://ieeexplore.ieee.org/document/5399169 | - |
| dc.identifier.wosid | 000273889600022 | - |
| dc.language | 영어 | - |
| dc.publisher | INST ENGINEERING TECHNOLOGY-IET | - |
| dc.title | Partial parallel encoder for IRA codes | - |
| dc.type | Article | - |
| dc.description.isOpenAccess | FALSE | - |
| dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
| dc.relation.journalResearchArea | Engineering | - |
| dc.type.docType | Article | - |
| dc.description.journalRegisteredClass | scie | - |
| dc.description.journalRegisteredClass | scopus | - |
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