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DC Field | Value | Language |
---|---|---|
dc.citation.endPage | 2512 | - |
dc.citation.number | 9 | - |
dc.citation.startPage | 2501 | - |
dc.citation.title | IEEE JOURNAL OF SOLID-STATE CIRCUITS | - |
dc.citation.volume | 54 | - |
dc.contributor.author | Seong, Taeho | - |
dc.contributor.author | Lee, Yongsun | - |
dc.contributor.author | Yoo, Seyeon | - |
dc.contributor.author | Choi, Jaehyouk | - |
dc.date.accessioned | 2023-12-21T18:44:51Z | - |
dc.date.available | 2023-12-21T18:44:51Z | - |
dc.date.created | 2019-09-16 | - |
dc.date.issued | 2019-09 | - |
dc.description.abstract | This paper presents a ring-type, digitally controlled oscillator (DCO)-based integer-N digital phase-locked loop (DPLL) that can achieve low jitter and low reference spur concurrently. In order to minimize the quantization error, while consuming a small amount of power, this work presents an optimal-threshold (OT) time-to-digital converter (TDC). The thresholds of the OT TPC and the phase-correction gain of the loop are corrected continuously in the background. The PLL was fabricated in a 65-nm CMOS process and its measured rms jitter integrated from 1 kHz to 100 MHz and the reference spur of a 2.4-GHz frequency were 320 fs and -75 dBc, respectively. Through measurement, they were verified to be maintained robustly over temperature and supply variations. The active area was 0.055 mm(2), and the power consumption was 6.0 mW. | - |
dc.identifier.bibliographicCitation | IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.54, no.9, pp.2501 - 2512 | - |
dc.identifier.doi | 10.1109/JSSC.2019.2918940 | - |
dc.identifier.issn | 0018-9200 | - |
dc.identifier.scopusid | 2-s2.0-85071582158 | - |
dc.identifier.uri | https://scholarworks.unist.ac.kr/handle/201301/27527 | - |
dc.identifier.url | https://ieeexplore.ieee.org/document/8737704 | - |
dc.identifier.wosid | 000482625000013 | - |
dc.language | 영어 | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | A 320-fs RMS Jitter and-75-dBc Reference-Spur Ring-DCO-Based Digital PLL Using an Optimal-Threshold TDC | - |
dc.type | Article | - |
dc.description.isOpenAccess | FALSE | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic | - |
dc.relation.journalResearchArea | Engineering | - |
dc.type.docType | Article | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.subject.keywordAuthor | Digital phase-locked loop (DPLL) | - |
dc.subject.keywordAuthor | jitter | - |
dc.subject.keywordAuthor | reference spur | - |
dc.subject.keywordAuthor | ring digitally controlled oscillator (DCO) | - |
dc.subject.keywordAuthor | time-to-digital converter (TDC) | - |
dc.subject.keywordPlus | LOW-PHASE-NOISE | - |
dc.subject.keywordPlus | LOW-POWER | - |
dc.subject.keywordPlus | LOOP | - |
dc.subject.keywordPlus | OSCILLATOR | - |
dc.subject.keywordPlus | DESIGN | - |
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