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Kim, Kyung Rok
Nano-Electronic Emerging Devices Lab.
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dc.citation.endPage 1503 -
dc.citation.number 19 -
dc.citation.startPage 1499 -
dc.citation.title IEICE ELECTRONICS EXPRESS -
dc.citation.volume 7 -
dc.contributor.author Cho, Seongjae -
dc.contributor.author Kang, In Man -
dc.contributor.author Kim, Kyung Rok -
dc.date.accessioned 2023-12-22T06:43:19Z -
dc.date.available 2023-12-22T06:43:19Z -
dc.date.created 2013-06-13 -
dc.date.issued 2010-10 -
dc.description.abstract We investigated the source-to-drain capacitance (C(sd)) due to DIBL effect of silicon nanowire (SNW) MOSFETs. Short-channel SNW devices operating at high drain voltages have the positive value of C(sd) by DIBL effect. On the other hand, junctionless SNW MOSFETs without source/drain (S/D) PN junctions have negative or zero values by small DIBL effect. By considering the additional source-to-drain capacitance component, the accuracy of a small-signal model was significantly improved on the imaginary part of Y(22)-parameter. -
dc.identifier.bibliographicCitation IEICE ELECTRONICS EXPRESS, v.7, no.19, pp.1499 - 1503 -
dc.identifier.doi 10.1587/elex.7.1499 -
dc.identifier.issn 1349-2543 -
dc.identifier.scopusid 2-s2.0-77958169171 -
dc.identifier.uri https://scholarworks.unist.ac.kr/handle/201301/2587 -
dc.identifier.url http://www.scopus.com/inward/record.url?partnerID=HzOxMe3b&scp=77958169171 -
dc.identifier.wosid 000282757200014 -
dc.language 영어 -
dc.publisher IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG -
dc.title Investigation of source-to-drain capacitance by DIBL effect of silicon nanowire MOSFETs -
dc.type Article -
dc.description.isOpenAccess TRUE -
dc.relation.journalWebOfScienceCategory Engineering, Electrical & Electronic -
dc.relation.journalResearchArea Engineering -
dc.description.journalRegisteredClass scie -
dc.description.journalRegisteredClass scopus -

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