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DC Field | Value | Language |
---|---|---|
dc.citation.endPage | 952 | - |
dc.citation.number | 5 | - |
dc.citation.startPage | 947 | - |
dc.citation.title | IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES | - |
dc.citation.volume | E96-A | - |
dc.contributor.author | Kang Yesung | - |
dc.contributor.author | Kim, Youngmin | - |
dc.date.accessioned | 2023-12-22T04:06:55Z | - |
dc.date.available | 2023-12-22T04:06:55Z | - |
dc.date.created | 2013-07-04 | - |
dc.date.issued | 2013-05 | - |
dc.description.abstract | Due to the increasing need for low-power circuits in mobile applications, numerous leakage and performance optimization techniques are being used in modern ICs. In the present paper, we propose a novel transistor-level technique to reduce leakage current while maintaining drive current. By slightly increasing the channel length at the edge of a device that exploits the edge effect, a leakage-optimized transistor can be produced. By using TCAD simulations, we analyze edge-length-biased transistors and then propose the optimal transistor shape for minimizing Ioff with the same or higher Ion current. Results show that by replacing all standard cells with their leakage-optimized counterparts, we can save up to 17% of the leakage in average for a set of benchmark circuits. | - |
dc.identifier.bibliographicCitation | IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, v.E96-A, no.5, pp.947 - 952 | - |
dc.identifier.doi | 10.1587/transfun.E96.A.947 | - |
dc.identifier.issn | 0916-8508 | - |
dc.identifier.scopusid | 2-s2.0-84878253313 | - |
dc.identifier.uri | https://scholarworks.unist.ac.kr/handle/201301/2525 | - |
dc.identifier.url | http://www.scopus.com/inward/record.url?partnerID=HzOxMe3b&scp=84878253313 | - |
dc.identifier.wosid | 000319085600014 | - |
dc.language | 영어 | - |
dc.publisher | IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG | - |
dc.title | Intra-gate length biasing for leakage optimization in 45nm technology node | - |
dc.type | Article | - |
dc.relation.journalWebOfScienceCategory | Computer Science, Hardware & Architecture; Computer Science, Information Systems; Engineering, Electrical & Electronic | - |
dc.relation.journalResearchArea | Computer Science; Engineering | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.subject.keywordAuthor | design for manufacturing (DFM) | - |
dc.subject.keywordAuthor | leakage saving | - |
dc.subject.keywordAuthor | non-rectangular transistor | - |
dc.subject.keywordAuthor | device model | - |
dc.subject.keywordAuthor | TCAD | - |
dc.subject.keywordAuthor | gate biasing | - |
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