Intra-gate length biasing for leakage optimization in 45nm technology node
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- Intra-gate length biasing for leakage optimization in 45nm technology node
- Kang Yesung; Kim, Youngmin
- Design for Manufacturing; Device models; Gate biasing; Leakage savings; TCAD
- Issue Date
- IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
- IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, v.E96-A, no.5, pp.947 - 952
- Due to the increasing need for low-power circuits in mobile applications, numerous leakage and performance optimization techniques are being used in modern ICs. In the present paper, we propose a novel transistor-level technique to reduce leakage current while maintaining drive current. By slightly increasing the channel length at the edge of a device that exploits the edge effect, a leakage-optimized transistor can be produced. By using TCAD simulations, we analyze edge-length-biased transistors and then propose the optimal transistor shape for minimizing Ioff with the same or higher Ion current. Results show that by replacing all standard cells with their leakage-optimized counterparts, we can save up to 17% of the leakage in average for a set of benchmark circuits.
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