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DC Field | Value | Language |
---|---|---|
dc.citation.endPage | 467 | - |
dc.citation.number | 4 | - |
dc.citation.startPage | 461 | - |
dc.citation.title | JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE | - |
dc.citation.volume | 18 | - |
dc.contributor.author | Ryu, Myunghwan | - |
dc.contributor.author | Kim, Youngmin | - |
dc.date.accessioned | 2023-12-21T20:18:29Z | - |
dc.date.available | 2023-12-21T20:18:29Z | - |
dc.date.created | 2018-09-19 | - |
dc.date.issued | 2018-08 | - |
dc.description.abstract | In this paper, a novel sandwiched-gate logic family that is based on a sandwiched-gate inverter, which consists of an NMOS Gate-All-Around (GAA) together with a donut-type PMOS GAA, is proposed. For the realization of the proposed vertical structure, a junctionless configuration is suggested with the absence of the channel- doping process. The ratio of the thickness of the NMOS and the PMOS determines the switching threshold in the sandwiched-gate inverter. The direct-current (DC) operation and the transient performance of the sandwiched-gate inverter are investigated with 3D technology computer-aided-design (TCAD) simulations. The sandwiched- gate inverter exhibits a correct inverter operation with a high noise margin and a fast transition speed. To extend the proposed architecture to other logic gates, the proposed sandwiched-gate structure is also applied to fundamental logic circuits such as the NAND, NOR, and SRAM cell designs, and each operation is verified. The proposed logic gates achieve up to a 20% area reduction compared with the conventional GAA. | - |
dc.identifier.bibliographicCitation | JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, v.18, no.4, pp.461 - 467 | - |
dc.identifier.doi | 10.5573/JSTS.2018.18.4.461 | - |
dc.identifier.issn | 1598-1657 | - |
dc.identifier.scopusid | 2-s2.0-85052399121 | - |
dc.identifier.uri | https://scholarworks.unist.ac.kr/handle/201301/24929 | - |
dc.identifier.url | http://www.dbpia.co.kr/Journal/ArticleDetail/NODE07521927 | - |
dc.identifier.wosid | 000442690300007 | - |
dc.language | 영어 | - |
dc.publisher | IEEK PUBLICATION CENTER | - |
dc.title | Junctionless Sandwiched-gate Logic Design using Novel Device Structure | - |
dc.type | Article | - |
dc.description.isOpenAccess | FALSE | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic; Physics, Applied | - |
dc.relation.journalResearchArea | Engineering; Physics | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.description.journalRegisteredClass | kci | - |
dc.subject.keywordAuthor | Sandwiched gate | - |
dc.subject.keywordAuthor | gate all around (GAA) | - |
dc.subject.keywordAuthor | inverter | - |
dc.subject.keywordAuthor | junctionless | - |
dc.subject.keywordAuthor | TCAD | - |
dc.subject.keywordAuthor | integrated circuits | - |
dc.subject.keywordPlus | FIELD-EFFECT TRANSISTORS | - |
dc.subject.keywordPlus | NANOWIRE TRANSISTORS | - |
dc.subject.keywordPlus | SI | - |
dc.subject.keywordPlus | PERFORMANCE | - |
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