There are no files associated with this item.
Full metadata record
DC Field | Value | Language |
---|---|---|
dc.citation.endPage | 2188 | - |
dc.citation.number | 12 | - |
dc.citation.startPage | 2180 | - |
dc.citation.title | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS | - |
dc.citation.volume | 63 | - |
dc.contributor.author | Kim, Changhyeon | - |
dc.contributor.author | Bong, Kyeongryeol | - |
dc.contributor.author | Choi, Sungpill | - |
dc.contributor.author | Lee, Kyuho Jason | - |
dc.contributor.author | Yoo, Hoi-Jun | - |
dc.date.accessioned | 2023-12-21T22:48:14Z | - |
dc.date.available | 2023-12-21T22:48:14Z | - |
dc.date.created | 2018-08-07 | - |
dc.date.issued | 2016-12 | - |
dc.description.abstract | A low-latency and low-power stereo matching accelerator is monolithically integrated with a CMOS image sensor (CIS) for mobile applications. To reduce the overall latency, focal-plane processing is adopted by using the proposed analog census transform circuit (ACTC), and the image readout is pipelined with the following stereo matching process. In addition, a novel focal-plane rectification pixel array (FRPA) merges the rectification with the image readout without any additional processing latency. For area-efficient pixel design, sparse rectification is proposed, and the image rectification is implemented with only two additional switches in each pixel. A stereo matching digital processor (SMDP) is integrated with the CIS for cost aggregation. We present the full design including the layout with a 65 nm CMOS process, and the FRPA, the ACTC, and the SMDP achieve 11.0 ms latency with complete stereo matching stages, which is suitable for a smooth user interface. As a result, the 2-chip stereo matching system dissipates 573.9 mu J/frame and achieves 17% energy reduction compared to a previous stereo matching SoC | - |
dc.identifier.bibliographicCitation | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v.63, no.12, pp.2180 - 2188 | - |
dc.identifier.doi | 10.1109/TCSI.2016.2619718 | - |
dc.identifier.issn | 1549-8328 | - |
dc.identifier.scopusid | 2-s2.0-84996939134 | - |
dc.identifier.uri | https://scholarworks.unist.ac.kr/handle/201301/24539 | - |
dc.identifier.url | https://ieeexplore.ieee.org/document/7745972/ | - |
dc.identifier.wosid | 000389338300009 | - |
dc.language | 영어 | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | A CMOS Image Sensor-Based Stereo Matching Accelerator With Focal-Plane Sparse Rectification and Analog Census Transform | - |
dc.type | Article | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
Items in Repository are protected by copyright, with all rights reserved, unless otherwise indicated.
Tel : 052-217-1404 / Email : scholarworks@unist.ac.kr
Copyright (c) 2023 by UNIST LIBRARY. All rights reserved.
ScholarWorks@UNIST was established as an OAK Project for the National Library of Korea.