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DC Field | Value | Language |
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dc.citation.endPage | 124 | - |
dc.citation.number | 1 | - |
dc.citation.startPage | 113 | - |
dc.citation.title | IEEE JOURNAL OF SOLID-STATE CIRCUITS | - |
dc.citation.volume | 50 | - |
dc.contributor.author | Kim, Gyeonghoon | - |
dc.contributor.author | Lee, Kyuho | - |
dc.contributor.author | Kim, Youchang | - |
dc.contributor.author | Park, Seongwook | - |
dc.contributor.author | Hong, Injoon | - |
dc.contributor.author | Bong, Kyeongryeol | - |
dc.contributor.author | Yoo, Hoi-Jun | - |
dc.date.accessioned | 2023-12-22T01:42:07Z | - |
dc.date.available | 2023-12-22T01:42:07Z | - |
dc.date.created | 2018-08-07 | - |
dc.date.issued | 2015-01 | - |
dc.description.abstract | Real-time augmented reality (AR) is actively studied for the future user interface and experience in high-performance head-mounted display (HMD) systems. The small battery size and limited computing power of the current HMD, however, fail to implement the real-time markerless AR in the HMD. In this paper, we propose a real-time and low-power AR processor for advanced 3D-AR HMD applications. For the high throughput, the processor adopts task-level pipelined SIMD-PE clusters and a congestion-aware network-on-chip (NoC). Both of these two features exploit the high data-level parallelism (DLP) and task-level parallelism (TLP) with the pipelined multicore architecture. For the low power consumption, it employs a vocabulary forest accelerator and a mixed-mode support vector machine (SVM)-based DVFS control to reduce unnecessary external memory accesses and core activation. The proposed 4 mm 8 mm HMD AR processor is fabricated using 65 nm CMOS technology for a battery-powered HMD platform with real-time AR operation. It consumes 381 mW average power and 778 mW peak power at 250 MHz operating frequency and 1.2 V supply voltage. It achieves 1.22 TOPS peak performance and 1.57 TOPS/W energy efficiency, which are, respectively, and higher than the state of the art. | - |
dc.identifier.bibliographicCitation | IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.50, no.1, pp.113 - 124 | - |
dc.identifier.doi | 10.1109/JSSC.2014.2352303 | - |
dc.identifier.issn | 0018-9200 | - |
dc.identifier.scopusid | 2-s2.0-84920144755 | - |
dc.identifier.uri | https://scholarworks.unist.ac.kr/handle/201301/24531 | - |
dc.identifier.url | https://ieeexplore.ieee.org/document/6899706/?arnumber=6899706 | - |
dc.identifier.wosid | 000346972800010 | - |
dc.language | 영어 | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | A 1.22 TOPS and 1.52 mW/MHz Augmented Reality Multicore Processor With Neural Network NoC for HMD Applications | - |
dc.type | Article | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.subject.keywordAuthor | Augmented reality (AR) | - |
dc.subject.keywordAuthor | AR processor architecture | - |
dc.subject.keywordAuthor | congestion-aware task assignment | - |
dc.subject.keywordAuthor | heterogeneous SIMD multicore architecture | - |
dc.subject.keywordAuthor | 2D-mesh network-on-chip | - |
dc.subject.keywordPlus | OBJECT RECOGNITION | - |
dc.subject.keywordPlus | ENGINE | - |
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