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DC Field | Value | Language |
---|---|---|
dc.citation.endPage | 300 | - |
dc.citation.number | 3 | - |
dc.citation.startPage | 295 | - |
dc.citation.title | JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE | - |
dc.citation.volume | 18 | - |
dc.contributor.author | Jang, Esan | - |
dc.contributor.author | Shin, Sunhae | - |
dc.contributor.author | Jeong, Jae Won | - |
dc.contributor.author | Kim, Kyung Rok | - |
dc.date.accessioned | 2023-12-21T20:39:57Z | - |
dc.date.available | 2023-12-21T20:39:57Z | - |
dc.date.created | 2018-07-13 | - |
dc.date.issued | 2018-06 | - |
dc.description.abstract | We propose a novel optimized design strategy by considering the correlated effects of high-kappa gate oxide and spacer dielectric on GIDL and DIBL for high performance nanoscale CMOS with III-V/Ge channel tri-gate FinFET structure. By investigating the transition of GIDL mechanism from vertical to lateral direction in 14-nm InAs n-FinFET and Ge p-FinFET with abrupt and high drain doping, the lateral GIDL is suppressed as 1/100 by high-kappa spacer with high drive current of 1 mA/um and lower leakage current than 100 nA/um which works on lower operation voltage (V-DD = 0.63 V). in addition, DIBL is also suppressed below 100 mV/V by taking relatively lower-K gate oxide than the high-kappa spacer. | - |
dc.identifier.bibliographicCitation | JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, v.18, no.3, pp.295 - 300 | - |
dc.identifier.doi | 10.5573/JSTS.2018.18.3.295 | - |
dc.identifier.issn | 1598-1657 | - |
dc.identifier.scopusid | 2-s2.0-85049003185 | - |
dc.identifier.uri | https://scholarworks.unist.ac.kr/handle/201301/24404 | - |
dc.identifier.url | http://www.dbpia.co.kr/Journal/ArticleDetail/NODE07469314 | - |
dc.identifier.wosid | 000436275900001 | - |
dc.language | 영어 | - |
dc.publisher | IEEK PUBLICATION CENTER | - |
dc.title | Low Leakage III-V/Ge CMOS FinFET Design for High-Performance Logic Applications with High-kappa Spacer Technology | - |
dc.type | Article | - |
dc.description.isOpenAccess | FALSE | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic; Physics, Applied | - |
dc.identifier.kciid | ART002355590 | - |
dc.relation.journalResearchArea | Engineering; Physics | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.description.journalRegisteredClass | kci | - |
dc.subject.keywordAuthor | Advanced CMOS | - |
dc.subject.keywordAuthor | low bandgap | - |
dc.subject.keywordAuthor | high mobility | - |
dc.subject.keywordAuthor | III-V semiconductor | - |
dc.subject.keywordAuthor | germanium | - |
dc.subject.keywordAuthor | GIDL | - |
dc.subject.keywordAuthor | DIBL | - |
dc.subject.keywordAuthor | FinFET | - |
dc.subject.keywordAuthor | high-k spacer | - |
dc.subject.keywordAuthor | well tempered design | - |
dc.subject.keywordPlus | MOSFETS | - |
dc.subject.keywordPlus | GIDL | - |
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