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DC Field | Value | Language |
---|---|---|
dc.citation.endPage | 858 | - |
dc.citation.number | 3 | - |
dc.citation.startPage | 849 | - |
dc.citation.title | IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY | - |
dc.citation.volume | 58 | - |
dc.contributor.author | Shringarpure, Ketan | - |
dc.contributor.author | Pan, Siming | - |
dc.contributor.author | Kim, Jingook | - |
dc.contributor.author | Fan, Jun | - |
dc.contributor.author | Achkir, Brice | - |
dc.contributor.author | Archambeault, Bruce | - |
dc.contributor.author | Drewniak, James L. | - |
dc.date.accessioned | 2023-12-21T23:38:55Z | - |
dc.date.available | 2023-12-21T23:38:55Z | - |
dc.date.created | 2017-01-10 | - |
dc.date.issued | 2016-06 | - |
dc.description.abstract | A methodology for modeling the power delivery network from the voltage regulator module to the pins of a high pin count integrated circuit on a printed circuit board (PCB) is presented. The proposed model is based on inductance extraction from first principle formulation of a cavity formed by parallel metal planes. Circuit reduction is used to practically realize the model for a production level, complex, multilayer PCBs. The lumped element model is compatible with SPICE-type simulators. The resulting model has a relatively simple circuit topology. The model is corroborated with microprobing measurements up to a few gigahertz. The model can be used for a wide range of geometry variations in a power integrity analysis, including complex power/ground stack up, various numbers of decoupling capacitors with arbitrary locations, numerous IC power pins and IC power/ground return via layouts, as well as hundreds of ground return vias. | - |
dc.identifier.bibliographicCitation | IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY, v.58, no.3, pp.849 - 858 | - |
dc.identifier.doi | 10.1109/TEMC.2016.2535459 | - |
dc.identifier.issn | 0018-9375 | - |
dc.identifier.scopusid | 2-s2.0-84979724814 | - |
dc.identifier.uri | https://scholarworks.unist.ac.kr/handle/201301/21188 | - |
dc.identifier.url | http://ieeexplore.ieee.org/document/7450658 | - |
dc.identifier.wosid | 000381433100026 | - |
dc.language | 영어 | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | Formulation and Network Model Reduction for Analysis of the Power Distribution Network in a Production-Level Multilayered Printed Circuit Board | - |
dc.type | Article | - |
dc.description.isOpenAccess | FALSE | - |
dc.relation.journalWebOfScienceCategory | Engineering, Electrical & Electronic; Telecommunications | - |
dc.relation.journalResearchArea | Engineering; Telecommunications | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.subject.keywordAuthor | Modeling PCB PDN | - |
dc.subject.keywordAuthor | power integrity | - |
dc.subject.keywordAuthor | printed circuit board power distribution network | - |
dc.subject.keywordPlus | INTEGRAL-EQUATION FORMULATION | - |
dc.subject.keywordPlus | SYSTEM-ON-PACKAGE | - |
dc.subject.keywordPlus | PLANE STRUCTURES | - |
dc.subject.keywordPlus | BUS DESIGN | - |
dc.subject.keywordPlus | INDUCTANCES | - |
dc.subject.keywordPlus | EXTRACTION | - |
dc.subject.keywordPlus | NOISE | - |
dc.subject.keywordPlus | EMI | - |
dc.subject.keywordPlus | TECHNOLOGY | - |
dc.subject.keywordPlus | ARRAYS | - |
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