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DC Field | Value | Language |
---|---|---|
dc.citation.number | 3 | - |
dc.citation.startPage | 51 | - |
dc.citation.title | ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS | - |
dc.citation.volume | 21 | - |
dc.contributor.author | Kim, Sangmin | - |
dc.contributor.author | Kang, Seokhyeong | - |
dc.contributor.author | Shin, Youngsoo | - |
dc.date.accessioned | 2023-12-21T23:37:51Z | - |
dc.date.available | 2023-12-21T23:37:51Z | - |
dc.date.created | 2016-06-29 | - |
dc.date.issued | 2016-07 | - |
dc.description.abstract | A dual-mode circuit is a circuit that has two operating modes: a default high-performance mode at nominal voltage and a secondary low-performance near-threshold voltage (NTV) mode. A key problem that we address is to maximize NTV mode clock frequency. Some cells that are particularly slow in NTV mode are optimized through transistor sizing and stack removal; static noise margin of each gate is extracted and appended in a library so that function failures can be checked and removed during synthesis. A new gate-sizing algorithm is proposed that takes account of timing slacks at both modes. A new sensitivity measure is introduced for this purpose; binary search is then applied to find the maximum NTV mode frequency. Clock-tree synthesis is reformulated to minimize clock skew at both modes. This is motivated by the fact that the proportion of load-dependent delay along clock paths, as well as clock-path delays themselves, should be made equal. Experiments on some test circuits indicate that NTV mode clock period is reduced by 24%, on average; clock skew at NTV decreases by 13%, on average; and NTV mode energy-delay product is reduced by 20%, on average. | - |
dc.identifier.bibliographicCitation | ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, v.21, no.3, pp.51 | - |
dc.identifier.doi | 10.1145/2856032 | - |
dc.identifier.issn | 1084-4309 | - |
dc.identifier.scopusid | 2-s2.0-84974588055 | - |
dc.identifier.uri | https://scholarworks.unist.ac.kr/handle/201301/19861 | - |
dc.identifier.url | http://dl.acm.org/citation.cfm?doid=2926747.2856032 | - |
dc.identifier.wosid | 000381424000016 | - |
dc.language | 영어 | - |
dc.publisher | ASSOC COMPUTING MACHINERY | - |
dc.title | Synthesis of dual-mode circuits through library design, gate sizing, and clock-tree optimization | - |
dc.type | Article | - |
dc.description.isOpenAccess | FALSE | - |
dc.relation.journalWebOfScienceCategory | Computer Science, Hardware & Architecture; Computer Science, Software Engineering | - |
dc.relation.journalResearchArea | Computer Science | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.subject.keywordAuthor | Clock-tree optimization | - |
dc.subject.keywordAuthor | Dual-mode circuit | - |
dc.subject.keywordAuthor | Gate sizing | - |
dc.subject.keywordAuthor | Near-threshold voltage | - |
dc.subject.keywordAuthor | Timing optimization | - |
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