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dc.citation.number 4 -
dc.citation.startPage 66 -
dc.citation.title ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS -
dc.citation.volume 20 -
dc.contributor.author Kahng, Andrew B. -
dc.contributor.author Kang, Seokhyeong -
dc.contributor.author Li, Jiajia -
dc.contributor.author De Gyvez, Jose Pineda -
dc.date.accessioned 2023-12-22T00:44:26Z -
dc.date.available 2023-12-22T00:44:26Z -
dc.date.created 2015-10-26 -
dc.date.issued 2015-09 -
dc.description.abstract Resilient design techniques are used to (i) ensure correct operation under dynamic variations and to (ii) improve design performance (e.g., timing speculation). However, significant overheads (e.g., 16% and 14% energy penalties due to throughput degradation and additional circuits) are incurred by existing resilient design techniques. For instance, resilient designs require additional circuits to detect and correct timing errors. Further, when there is an error, the additional cycles needed to restore a previous correct state degrade throughput, which diminishes the performance benefit of using resilient designs. In this work, we describe an improved methodology for resilient design implementation to minimize the costs of resilience in terms of power, area, and throughput degradation. Our methodology uses two levers: selective-endpoint optimization (i. e., sensitivity-based margin insertion) and clock skew optimization. We integrate the two optimization techniques in an iterative optimization flow which comprehends toggle rate information and the trade-off between cost of resilience and margin on combinational paths. Since the error-detection network can result in up to 9% additional wirelength cost, we also propose a matching-based algorithm for construction of the error-detection network to minimize this resilience overhead. Further, our implementations comprehend the impacts of signoff corners (in particular, hold constraints, and use of typical vs. slow libraries) and process variation, which are typically omitted in previous studies of resilience trade-offs. Our proposed flow achieves energy reductions of up to 21% and 10% compared to a conventional (with only margin used to attain robustness) design and a brute-force implementation (i.e., a typical resilient design, where resilient endpoints are (greedily) instantiated at timing-critical endpoints), respectively. We show that these benefits increase in the context of an adaptive voltage scaling strategy -
dc.identifier.bibliographicCitation ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, v.20, no.4, pp.66 -
dc.identifier.doi 10.1145/2749462 -
dc.identifier.issn 1084-4309 -
dc.identifier.scopusid 2-s2.0-84942891363 -
dc.identifier.uri https://scholarworks.unist.ac.kr/handle/201301/17582 -
dc.identifier.url http://dl.acm.org/citation.cfm?doid=2830627.2749462 -
dc.identifier.wosid 000362344900020 -
dc.language 영어 -
dc.publisher ASSOC COMPUTING MACHINERY -
dc.title An Improved Methodology for Resilient Design Implementation -
dc.type Article -
dc.description.isOpenAccess FALSE -
dc.relation.journalWebOfScienceCategory Computer Science, Hardware & Architecture; Computer Science, Software Engineering -
dc.relation.journalResearchArea Computer Science -
dc.description.journalRegisteredClass scie -
dc.description.journalRegisteredClass scopus -
dc.subject.keywordAuthor Design -
dc.subject.keywordAuthor Resilience -
dc.subject.keywordAuthor energy reduction -
dc.subject.keywordAuthor design optimization -
dc.subject.keywordPlus DYNAMIC VARIATION TOLERANCE -
dc.subject.keywordPlus SITU ERROR-DETECTION -
dc.subject.keywordPlus TIMING SPECULATION -
dc.subject.keywordPlus EFFICIENT -
dc.subject.keywordPlus PATH -
dc.subject.keywordPlus PROCESSOR -
dc.subject.keywordPlus CIRCUITS -

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