Compact Design of Low Power Standard Ternary Inverter Based on OFF-State Current Mechanism Using Nano-CMOS Technology

Abstract

We propose a novel standard ternary inverter (STI) based on nanoscale CMOS technology for a compact design of multivalued logic. Using the gate bias independent OFF-state mechanisms of junction band-to-band tunneling (BTBT), tristate STI operation has been demonstrated in the conventional binary CMOS inverter by TCAD device and mixed-mode circuit simulation with 32-nm high-kappa/metal-gate technology. Through analytical device modeling on BTBT and subthreshold current, static noise margin (SNM), off-leakage variation (OLV), and operation voltage (V-DD) scaling limits of STI have been investigated. The typical SNM is 200 mV and the variability of the intermediate level (Delta V-OM similar to 50 mV) from OLV can be allowable into the worst SNM (>100 mV) of STI operation at V-DD = 1 V. Exponentially reduced BTBT off-leakage around minimum V-DD similar to 0.1 V is promising for ultimate low-power application of our STI