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Lee, Myunghee
Automotive Electronic Systems and Semiconductor Lab
Research Interests
  • Automotive Electronic System Design
  • Automtoive Semicondutor IC design

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A Piecewise Linear 10 Bit DAC Architecture With Drain Current Modulation for Compact LCD Driver ICs

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Title
A Piecewise Linear 10 Bit DAC Architecture With Drain Current Modulation for Compact LCD Driver ICs
Author
Jeon, Yong-JoonLee, Hyung-MinLee, Sung-WooCho, Gyu-HyeongKim, Hyoung RaeChoi, Yoon-KyungLee, Myunghee
Keywords
Cascaded-dividing DAC;  data driver;  drain current modulation;  interpolation;  LCD;  piecewise linear
Issue Date
2009-12
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Citation
IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.44, no.12, pp.3659 - 3675
Abstract
A piecewise linear 10 bit DAC for LCD data driver with robust interpolation method of drain current modulation is presented. It has higher effective bit resolution than the linear 10 bit switched-capacitor DAC when applied to nonlinear liquid crystal characteristics. By adopting a simultaneous design flow based on the estimations for the mismatch and nonlinearity effects on channel driver performance, the proposed DAC accomplishes good DNL of 0.37 LSB and excellent channel uniformity such that the mean and the standard deviation of the maximum output voltage deviations are 6.35 mV and 0.54 mV, respectively. The data driver with the new interpolation shows 8.2% shrinkage of chip area in comparison with the conventional 8 bit data driver with R-DAC
URI
https://scholarworks.unist.ac.kr/handle/201301/12568
DOI
10.1109/JSSC.2009.2035547
ISSN
0018-9200
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