A Piecewise Linear 10 Bit DAC Architecture With Drain Current Modulation for Compact LCD Driver ICs
Cited 8 times inCited 10 times in
- A Piecewise Linear 10 Bit DAC Architecture With Drain Current Modulation for Compact LCD Driver ICs
- Jeon, Yong-Joon; Lee, Hyung-Min; Lee, Sung-Woo; Cho, Gyu-Hyeong; Kim, Hyoung Rae; Choi, Yoon-Kyung; Lee, Myunghee
- Cascaded-dividing DAC; data driver; drain current modulation; interpolation; LCD; piecewise linear
- Issue Date
- IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
- IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.44, no.12, pp.3659 - 3675
- A piecewise linear 10 bit DAC for LCD data driver with robust interpolation method of drain current modulation is presented. It has higher effective bit resolution than the linear 10 bit switched-capacitor DAC when applied to nonlinear liquid crystal characteristics. By adopting a simultaneous design flow based on the estimations for the mismatch and nonlinearity effects on channel driver performance, the proposed DAC accomplishes good DNL of 0.37 LSB and excellent channel uniformity such that the mean and the standard deviation of the maximum output voltage deviations are 6.35 mV and 0.54 mV, respectively. The data driver with the new interpolation shows 8.2% shrinkage of chip area in comparison with the conventional 8 bit data driver with R-DAC
- Appears in Collections:
- EE_Journal Papers
- Files in This Item:
- There are no files associated with this item.
can give you direct access to the published full text of this article. (UNISTARs only)
Show full item record
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.