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DC Field | Value | Language |
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dc.citation.endPage | 417 | - |
dc.citation.number | 3 | - |
dc.citation.startPage | 404 | - |
dc.citation.title | IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS | - |
dc.citation.volume | 31 | - |
dc.contributor.author | Kahng, Andrew B. | - |
dc.contributor.author | Kang, Seokhyeong | - |
dc.contributor.author | Kumar, Rakesh | - |
dc.contributor.author | Sartori, John | - |
dc.date.accessioned | 2023-12-22T05:15:53Z | - |
dc.date.available | 2023-12-22T05:15:53Z | - |
dc.date.created | 2015-07-03 | - |
dc.date.issued | 2012-03 | - |
dc.description.abstract | Conventional computer-aided design (CAD) methodologies optimize a processor module for correct operation and prohibit timing violations during nominal operation. We propose recovery-driven design, a design approach that optimizes a processor module for a target timing error rate (ER) instead of correct operation. The target ER is chosen based on how many errors can be gainfully tolerated by a hardware or software error resilience mechanism. We show that significant power benefits are possible from a recovery-driven design approach that deliberately allows errors caused by voltage overscaling to occur during nominal operation, while relying on an error resilience technique to tolerate these errors. We present a detailed evaluation and analysis of such a CAD methodology that minimizes the power of a processor module for a target ER. We show how this design-level methodology can be extended to design recovery-driven processors-processors that are optimized to take advantage of hardware or software error resilience. We also discuss a gradual slack recovery-driven design approach that optimizes for a range of ERs to create soft processors-processors that have graceful failure characteristics and the ability to trade throughput or output quality for additional energy savings over a range of ERs. We demonstrate significant power benefits over conventional design-11.8% on average over all modules and ER targets, and up to 29.1% for individual modules. Processor-level benefits were 19.0%, on average. Benefits increase when recovery-driven design is coupled with an error resilience mechanism or when the number of available voltage domains increases | - |
dc.identifier.bibliographicCitation | IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, v.31, no.3, pp.404 - 417 | - |
dc.identifier.doi | 10.1109/TCAD.2011.2172610 | - |
dc.identifier.issn | 0278-0070 | - |
dc.identifier.scopusid | 2-s2.0-84863411602 | - |
dc.identifier.uri | https://scholarworks.unist.ac.kr/handle/201301/11875 | - |
dc.identifier.url | http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6152777&tag=1 | - |
dc.identifier.wosid | 000300513500007 | - |
dc.language | 영어 | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | Recovery-Driven Design: Exploiting Error Resilience in Design of Energy-Efficient Processors | - |
dc.type | Article | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.subject.keywordAuthor | Cell sizing | - |
dc.subject.keywordAuthor | error resilience | - |
dc.subject.keywordAuthor | power minimization | - |
dc.subject.keywordAuthor | recovery-driven design | - |
dc.subject.keywordAuthor | slack redistribution | - |
dc.subject.keywordPlus | RUNTIME-LEAKAGE CONTROL | - |
dc.subject.keywordPlus | TRADEOFFS | - |
dc.subject.keywordPlus | CIRCUITS | - |
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