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Kang, Seokhyeong
System-on-Chip Design Lab
Research Interests
  • System-on-Chip, low power, computer-aided design, physical implementation

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Recovery-Driven Design: Exploiting Error Resilience in Design of Energy-Efficient Processors

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dc.contributor.author Kahng, Andrew B. ko
dc.contributor.author Kang, Seokhyeong ko
dc.contributor.author Kumar, Rakesh ko
dc.contributor.author Sartori, John ko
dc.date.available 2015-07-03T06:35:59Z -
dc.date.created 2015-07-03 ko
dc.date.issued 2012-03 -
dc.identifier.citation IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, v.31, no.3, pp.404 - 417 ko
dc.identifier.issn 0278-0070 ko
dc.identifier.uri https://scholarworks.unist.ac.kr/handle/201301/11875 -
dc.identifier.uri http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6152777&tag=1 ko
dc.description.abstract Conventional computer-aided design (CAD) methodologies optimize a processor module for correct operation and prohibit timing violations during nominal operation. We propose recovery-driven design, a design approach that optimizes a processor module for a target timing error rate (ER) instead of correct operation. The target ER is chosen based on how many errors can be gainfully tolerated by a hardware or software error resilience mechanism. We show that significant power benefits are possible from a recovery-driven design approach that deliberately allows errors caused by voltage overscaling to occur during nominal operation, while relying on an error resilience technique to tolerate these errors. We present a detailed evaluation and analysis of such a CAD methodology that minimizes the power of a processor module for a target ER. We show how this design-level methodology can be extended to design recovery-driven processors-processors that are optimized to take advantage of hardware or software error resilience. We also discuss a gradual slack recovery-driven design approach that optimizes for a range of ERs to create soft processors-processors that have graceful failure characteristics and the ability to trade throughput or output quality for additional energy savings over a range of ERs. We demonstrate significant power benefits over conventional design-11.8% on average over all modules and ER targets, and up to 29.1% for individual modules. Processor-level benefits were 19.0%, on average. Benefits increase when recovery-driven design is coupled with an error resilience mechanism or when the number of available voltage domains increases ko
dc.description.statementofresponsibility close -
dc.language ENG ko
dc.publisher IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC ko
dc.subject Cell sizing ko
dc.subject error resilience ko
dc.subject power minimization ko
dc.subject recovery-driven design ko
dc.subject slack redistribution ko
dc.title Recovery-Driven Design: Exploiting Error Resilience in Design of Energy-Efficient Processors ko
dc.type ARTICLE ko
dc.identifier.scopusid 2-s2.0-84863411602 ko
dc.identifier.wosid 000300513500007 ko
dc.type.rims ART ko
dc.description.wostc 3 *
dc.description.scopustc 4 *
dc.date.tcdate 2015-12-28 *
dc.date.scptcdate 2015-11-04 *
dc.identifier.doi 10.1109/TCAD.2011.2172610 ko
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