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Kim, Jae Joon
Circuits & Systems Design Lab (CSDL)
Research Interests
  • Integrated circuits and systems, smart sensor interfaces, wearable healthcare systems, IoT & automotive electronics, mixed-mode circuits

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A low-jitter mixed-mode DLL for high-speed DRAM applications

Cited 27 times inthomson ciCited 31 times inthomson ci
Title
A low-jitter mixed-mode DLL for high-speed DRAM applications
Author
Kim, Jae JoonLee, Sang-BoJung, Tae-SungKim, Chang-HyunCho, Soo-InKim, Beomsup
Issue Date
2000-10
Publisher
IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Citation
IEEE JOURNAL OF SOLID-STATE CIRCUITS, v.35, no.10, pp.1430 - 1436
Abstract
This paper presents a salient clock deskewing method with a mixed-mode delay-locked loop (MDLL) for high-speed synchronous DRAM applications. The presented method not only solves the resolution problem of conventional digital deskewing circuits, but also improves the jitter performance to the le, el of well-designed analog deskewing circuits, while keeping the power consumption and locking speed of digital deskewing circuits. The whole deskewing circuit is fabricated in a 3.3-V 0.6-mu m triple-metal CMOS process and occupies a die area of 0.45 mm(2), Measured rms jitter is 6.38 ps, The power consumption of the entire chip, including I/O peripherals, is 33 mW at 200 MHz with a 3.3-V supply.
URI
https://scholarworks.unist.ac.kr/handle/201301/10808
URL
http://www.scopus.com/inward/record.url?partnerID=HzOxMe3b&scp=0034296002
ISSN
0018-9200
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