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Kim, Jae Joon
Circuits & Systems Design Lab (CSDL)
Research Interests
  • Integrated circuits and systems, smart sensor interfaces, wearable healthcare systems, IoT & automotive electronics, mixed-mode circuits

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Analysis and Design of Multistage Low-Phase-Noise CMOS LC-Ring Oscillators

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Title
Analysis and Design of Multistage Low-Phase-Noise CMOS LC-Ring Oscillators
Author
Kim, Jae JoonLim, Jae SangKim, Beomsup
Issue Date
2005-04
Publisher
IEICE-INST ELECTRONICS INFORMATION COMMUNICATIONS ENG
Citation
IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, v.E88-A, no.4, pp.1084 - 1089
Abstract
A novel CMOS LC oscillator architecture combining an LC tuned oscillator and a ring structure is presented as a new design topology to deliver improved phase noise for multiphase applications. The relative enhancement in the phase noise is estimated using a linear noise modeling approach. A three-stage LC-ring oscillator fabricated in a 0.6 mm CMOS technology achieves measured phase noise of -132 dBc/Hz at 600 kHz offset from a 900 MHz carrier and dissipates 20 mW with a 2.5 V power supply.
URI
https://scholarworks.unist.ac.kr/handle/201301/10046
DOI
10.1093/ietfec/e88-a.4.1084
ISSN
0916-8508
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