https://scholarworks.unist.ac.kr/handle/201301/41 Wed, 08 Apr 2026 21:16:52 GMT 2026-04-08T21:16:52Z https://scholarworks.unist.ac.kr/handle/201301/90971 Title: Low Power Edge - AI Platform Integrating a VCO - Based Sigma – Delta RDC and a Reconfigurable Analog TCN Author(s): Hwang, Jaeseong Abstract: Continuous environmental and biomedical monitoring requires sensor nodes that operate with minimal energy, cover wide input dynamics, and perform local decision-making without relying on power-hungry data converters or off-chip processors. However, practical sensor interfaces must simultaneously tolerate large variations in signal amplitude and timescale—ranging from slow- changing chemical resistive sensors to faster physiological waveforms—while maintaining accuracy under strict power budgets. To address these constraints, this thesis presents a low-power edge-AI platform that integrates (1) a wide-range resistive sensor readout IC (ROIC) based on a VCO-based sigma–delta (ΣΔ) resistor-to-digital converter (RDC) with adaptive voltage selection, and (2) a reconfigurable analog temporal convolutional network (TCN) classifier for real-time anomaly/event detection. The proposed ROIC targets low-resistance (low-R) and wide dynamic-range sensing where conventional resistive front-ends suffer from large bias currents, self-heating, and unstable reference generation, which can degrade both sensor integrity and conversion linearity. The RDC employs a voltage-regulated front-end with a first-order ΣΔ loop and a VCO-based integration/phase quantization stage. In particular, an adaptive voltage selector dynamically adjusts the reference level to keep the converter within an optimal operating window across large resistance variations, enabling stable conversion gain and suppressing error growth at the extremes of the measurable range. The architecture further supports a compact digital output interface through phase quantization and downstream bit reduction, allowing efficient off-chip readout and resistance reconstruction. Measurement results demonstrate a resistance readout range of 500 Ω to 500 kΩ with 293 µW power consumption, achieving 13.19-bit ENOB and 81.20 dB SNR, validating suitability for wide-range environmental sensing including low-R chemiresistor sensors. To enable on-node intelligence under tight power and area budgets, this work further proposes a charge-sharing MAC–based analog TCN that provides long receptive-field inference with programmable sampling and flexible analog/digital operation modes. Unlike fixed-function analog CNN accelerators that are often optimized for a single sampling condition or limited receptive field, the proposed processor maps dilated temporal convolutions onto a compact, reusable computation fabric. Programmable sampling and layer-wise operating scenarios allow the same hardware core to adapt across applications with different bandwidth and memory-retention requirements, while analog/digital memory partitioning provides an additional knob to trade off leakage robustness, throughput, and energy. A 4-channel depth-wise architecture with 256 input samples and 4 layers is realized with a compact parameter count (1.7k), demonstrating parameter-efficient feature extraction suitable for always-on operation. System-level validation shows robust classification performance on representative datasets, including arrhythmia detection on ECG (MIT-BIH dataset) with 0.9593 accuracy and 0.9377 sensitivity, and gas event detection (UCI Irvine CO gas dataset) with 0.9415 accuracy and 0.9710 sensitivity. By co-designing a wide-range, low-power resistive sensing front-end and a reconfigurable analog inference back-end, this thesis demonstrates an integrated approach toward scalable 24/7 edge sensing platforms capable of real-time detection under stringent energy constraints, and provides a pathway toward multi- domain sensor intelligence using a unified mixed-signal hardware framework. Major: Department of Electrical Engineering Sat, 31 Jan 2026 15:00:00 GMT https://scholarworks.unist.ac.kr/handle/201301/90971 2026-01-31T15:00:00Z https://scholarworks.unist.ac.kr/handle/201301/90970 Title: Learned Volume Compression for Dynamic TSDF Sequences Author(s): Choi, Junho Abstract: This paper introduces a novel lossy compression method for Truncated Signed Distance Function (TSDF) sequences, a common 3D representation. To date, research on compressing 3D TSDF videos has been notably scarce. Our work aims to fill this gap by proposing an approach analogous to JPEG and MPEG methodologies. Keyframes (I-Frames) are compressed using a new intraframe codec, while intermediate frames are predicted using RAFT (Recurrent All-Pairs Field Transforms) [1] and subsequently corrected through a refinement process. Major: Department of Electrical Engineering Sat, 31 Jan 2026 15:00:00 GMT https://scholarworks.unist.ac.kr/handle/201301/90970 2026-01-31T15:00:00Z https://scholarworks.unist.ac.kr/handle/201301/90969 Title: Bias-Temperature Instability Characteristics of High-k Metal Gate Ternary CMOS Technology Author(s): Jang, Injun Abstract: As CMOS technology approaches its power scaling limits, multi-valued logic has emerged as a promising alternative to improve energy efficiency and integration density. Among them, Ternary CMOS (T-CMOS) offers significant advantages; however, its practical deployment critically depends on the long-term reliability of the underlying devices, particularly under bias temperature instability (BTI). Due to reduced noise margins and the presence of intermediate logic states, BTI-induced threshold voltage degradation poses a more severe reliability challenge in T-CMOS than in conventional binary CMOS. In this work, the BTI characteristics of high-k metal gate (HKMG) MOSFETs fabricated for Ternary CMOS operation are systematically investigated. The physical components of BTI degradation are defined and analyzed, including interface trap generation (ΔNIT), pre-existing charge trapping (ΔNHT, ΔNET), and oxide-bulk trap generation(ΔNOT). An experimental extraction methodology is established based on C–V calibration and midgap- based stress voltage selection to minimize ΔVOT contributions. NBTI and PBTI behaviors are evaluated over a several conditions of gate voltage, temperature, and stress time conditions. The results show that both ternary and binary CMOS devices exhibit similar BTI degradation kinetics, indicating identical underlying physical mechanisms. However, ternary devices demonstrate distinct degradation characteristics arising from differences in pre-existing trap conditions rather than mechanism changes. Flicker noise measurements reveal an increased density of pre-existing traps in ternary CMOS devices, which significantly affect BTI behavior by enhancing charge trapping during stress and modifying voltage and time acceleration characteristics. While NBTI exhibits an increased ΔVIT due to enhanced interface damage induced by increased halo implant, a trapping-dominant degradation regime is observed in PBTI, leading to reduced voltage acceleration factors and time exponents without introducing new degradation mechanisms. Based on experimentally extracted BTI parameters and initial trap densities, using empirical model lifetime prediction framework is implemented to estimate the 10-year threshold voltage shift at nominal operating voltage. The results provide a quantitative assessment of long-term reliability for ternary CMOS devices under realistic use conditions. This study demonstrates that increasing in halo implantation does not change the physical mechanisms of BTI components and provides a quantitative analysis of their impact on the reliability of ternary CMOS devices. Major: Department of Electrical Engineering Sat, 31 Jan 2026 15:00:00 GMT https://scholarworks.unist.ac.kr/handle/201301/90969 2026-01-31T15:00:00Z https://scholarworks.unist.ac.kr/handle/201301/90968 Title: Dynamic Risk Estimation and Mapping for Reinforcement Learning-Based Safe Robot Navigation in Dense Crowds Author(s): Lee, Hyojae Abstract: In this thesis, we explore the field of robot navigation, specifically the fundamental challenge of ensuring safe and efficient operation in environments shared with dense pedestrian crowds. While advances in deep learning offer promising methods to predict human trajectories, previous approaches that directly incorporate these predictions into the control policy may compromise safety. This is due to the inherent uncertainty of human motion, which can make any single predicted path unreliable. To bridge this gap, this thesis proposes a novel deep reinforcement learning (DRL) framework that enables a mobile robot to navigate safely and efficiently through spaces with both static obstacles and dense pedestrian crowds by explicitly reasoning about predictive uncertainty. The policy generates control commands based on a unique state representation: a spatio-temporal risk map that fuses the static environment with the uncertainty of pedestrian predictions. To learn how to utilize this rich representation effectively, the policy is trained end-to-end with a novel reward function inspired by Model Predictive Control (MPC), guiding it to develop proactive behaviors based on the risk map. Through a series of experiments in diverse pedestrian-dense environments, we demonstrate that our framework achieves higher success rates and efficiency compared to state-of-the-art methods. Major: Department of Electrical Engineering Sat, 31 Jan 2026 15:00:00 GMT https://scholarworks.unist.ac.kr/handle/201301/90968 2026-01-31T15:00:00Z