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    <title>Repository Collection:</title>
    <link>https://scholarworks.unist.ac.kr/handle/201301/39</link>
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        <rdf:li rdf:resource="https://scholarworks.unist.ac.kr/handle/201301/91115" />
        <rdf:li rdf:resource="https://scholarworks.unist.ac.kr/handle/201301/90271" />
        <rdf:li rdf:resource="https://scholarworks.unist.ac.kr/handle/201301/89996" />
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    <dc:date>2026-04-04T18:11:47Z</dc:date>
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  <item rdf:about="https://scholarworks.unist.ac.kr/handle/201301/91115">
    <title>Active BSCDN Benchmark Framework with Backside-Compatible CNFET Logic Technology</title>
    <link>https://scholarworks.unist.ac.kr/handle/201301/91115</link>
    <description>Title: Active BSCDN Benchmark Framework with Backside-Compatible CNFET Logic Technology
Author(s): Shin, Yehyun; Kim, Ikkyum; Park, Minho; Yoon, Junghyun; Baek, Seunghun; Eum, Seongmin; Yang, Heesoo; Choi, Yurim; Jeong, Jaeyong; Kim, Sanghyeon; Jung, Haksoon; Kim, Seongju; Park, Heechun; Kwon, Jimin
Abstract: This study presents a benchmark framework for digital blocks featuring an active backside clock distribution network (BSCDN), which incorporates clock buffers and sinks implemented using backside-compatible logic based on carbon nanotube field-effect transistors (CNFETs). The proposed framework includes the fabrication, characterization and TCAD modeling of complementary CNFETs, neural network-based compact modeling, standard cell characterization, and a block-level benchmark comparing the performance of the active BSCDN with that of reported passive CDNs.</description>
    <dc:date>2025-12-05T15:00:00Z</dc:date>
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  <item rdf:about="https://scholarworks.unist.ac.kr/handle/201301/90271">
    <title>SPIMA: Scalable and Cost-Efficient Sparse Matrix Multiplication via Processing in DRAM Array</title>
    <link>https://scholarworks.unist.ac.kr/handle/201301/90271</link>
    <description>Title: SPIMA: Scalable and Cost-Efficient Sparse Matrix Multiplication via Processing in DRAM Array
Author(s): Assylbekov, Tairali; Yu, Minsang; Park, Jaewoo; Kim, Mingon; Kim, Seungsu; Lee, Jongeun</description>
    <dc:date>2025-10-25T15:00:00Z</dc:date>
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  <item rdf:about="https://scholarworks.unist.ac.kr/handle/201301/89996">
    <title>Introduction to UNIST FAB Infrastructure and Open Service for Quantum Integrated Photonic Devices: Equipment and Process Technology</title>
    <link>https://scholarworks.unist.ac.kr/handle/201301/89996</link>
    <description>Title: Introduction to UNIST FAB Infrastructure and Open Service for Quantum Integrated Photonic Devices: Equipment and Process Technology
Author(s): Park, Kibog; Shin, Heedeuk; Kim, Jehyung; Kwon, Min-Suk; Lee, Jongwon; Chung, Il-Sug
Abstract: As an initiative for constructing a nationwide quantum FAB infrastructure, the UNIST-POSTECH consortium has been awarded a three-year government project in 2023, intended to equip the UNST FAB with the cutting-edge fabrication apparatuses and process technologies for quantum integrated photonic devices. In this talk, an overview of the project will be given including its main objective, fabrication apparatuses to be installed and associated process technologies to be developed, and up-to-date progress reports. Additionally, the detailed time table to kick off providing the open service for utilizing the installed apparatuses and developed processes to the domestic researchers working on quantum technology will also be presented.</description>
    <dc:date>2025-02-10T15:00:00Z</dc:date>
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  <item rdf:about="https://scholarworks.unist.ac.kr/handle/201301/89897">
    <title>InAs/AlSb Heterostructures for Enhanced Second Harmonic Generation Polaritonic Metasurface within the SWIR</title>
    <link>https://scholarworks.unist.ac.kr/handle/201301/89897</link>
    <description>Title: InAs/AlSb Heterostructures for Enhanced Second Harmonic Generation Polaritonic Metasurface within the SWIR
Author(s): Kim, Mingyun; Lee, Jongwon</description>
    <dc:date>2025-02-11T15:00:00Z</dc:date>
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