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  <channel rdf:about="https://scholarworks.unist.ac.kr/handle/201301/37">
    <title>Repository Community:</title>
    <link>https://scholarworks.unist.ac.kr/handle/201301/37</link>
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        <rdf:li rdf:resource="https://scholarworks.unist.ac.kr/handle/201301/91349" />
        <rdf:li rdf:resource="https://scholarworks.unist.ac.kr/handle/201301/91341" />
        <rdf:li rdf:resource="https://scholarworks.unist.ac.kr/handle/201301/91256" />
        <rdf:li rdf:resource="https://scholarworks.unist.ac.kr/handle/201301/91249" />
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    <dc:date>2026-04-19T14:10:15Z</dc:date>
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  <item rdf:about="https://scholarworks.unist.ac.kr/handle/201301/91349">
    <title>Indium Tin Oxide Vertical Channel Transistors for Scaled 4F2 2T0C Gain Cell Memory With Etched Sidewall Cleaning</title>
    <link>https://scholarworks.unist.ac.kr/handle/201301/91349</link>
    <description>Title: Indium Tin Oxide Vertical Channel Transistors for Scaled 4F2 2T0C Gain Cell Memory With Etched Sidewall Cleaning
Author(s): Gu, Hyeonho; Jung, Haksoon; Park, Minho; Lee, Hyeonjin; Choi, Ae Rim; Oh, Il-Kwon; Zhao, Yanfeng; Kim, Byungjo; Kim, Jungsik; Jang, Byung Chul; Lee, Yongwoo; Kwon, Jimin
Abstract: 2T0C gain cell memory based on amorphous oxide semiconductor vertical channel transistors (VCTs) has emerged as a promising high-density embedded dynamic access memory solution for memory-centric computing systems, monolithically integrated atop silicon logic. This capacitor-less memory offers long retention time and a compact 4F(2) cell footprint, enabling low-power and area-efficient integration above logic circuits. In this work, amorphous indium tin oxide VCTs and 2T0C gain cells with hole diameters scaled down to 150 nm were fabricated. However, scaling the hole diameter caused residual etch by-products to accumulate along the channel sidewalls, degrading the subthreshold swing and on-state current. To mitigate this issue, a sidewall cleaning process was introduced to effectively remove the residues. The treatment improved the VCT on-state current by over three orders of magnitude and enabled stable single- and two-bit memory operation with retention time exceeding 160 s.</description>
    <dc:date>2026-03-31T15:00:00Z</dc:date>
  </item>
  <item rdf:about="https://scholarworks.unist.ac.kr/handle/201301/91341">
    <title>All-Dielectric Metasurface with a Two-Dimensional Locally Flat Photonic Band</title>
    <link>https://scholarworks.unist.ac.kr/handle/201301/91341</link>
    <description>Title: All-Dielectric Metasurface with a Two-Dimensional Locally Flat Photonic Band
Author(s): Tara, Virat; Munley, Christopher; Manna, Arnab; Froch, Johannes; Barnard, Arthur; Choi, Minho; Majumdar, Arka
Abstract: Photonic flatbands offer promising light-matter interaction due to their unique slow-light nature. In recent years, flatbands have also attracted significant interest in optical engineering because of their angle-insensitive resonant characteristics. However, to date, no studies have reported the dispersionless behavior of flatbands under arbitrary two-dimensional incident angles and polarizations. Here, we present a two-dimensional photonic flatband created using a silicon metasurface with a Lieb lattice-inspired structure that demonstrates a locally flat photonic band for both transverse electric (S-) and transverse magnetic (P-) polarized light. Employing Fourier imaging, we analyze the energy-momentum relation of the flatband metasurface under arbitrary two-dimensional incident angles, demonstrating flatbands with dispersion (change in resonance) less than the resonance line width up to a numerical aperture of 0.22 (polar angle theta = +/- 12.7 degrees) for all polarizations and arbitrary azimuthal angles (phi). The maximum flatband extent goes up to 0.6 (theta = +/- 36.8 degrees) for p-polarization at phi = 0 degrees in the experiment. This geometry can be adapted for various applications in local field enhancement, reconfigurable metasurfaces, enhanced photodetection, and augmented reality displays.</description>
    <dc:date>2026-02-28T15:00:00Z</dc:date>
  </item>
  <item rdf:about="https://scholarworks.unist.ac.kr/handle/201301/91256">
    <title>Achievable rate analysis of orbital angular momentum multiplexing and demultiplexing using E-band metasurfaces</title>
    <link>https://scholarworks.unist.ac.kr/handle/201301/91256</link>
    <description>Title: Achievable rate analysis of orbital angular momentum multiplexing and demultiplexing using E-band metasurfaces
Author(s): Chung, Hyeongju; Kim, Beomjoon; Lee, Young-Seok; Choi, Hongeun; Jung, Bang Chul; Choi, EunMi; Lee, Jongwon
Abstract: To meet the growing demand for high-capacity wireless communications, orbital angular momentum (OAM) multiplexing has garnered significant attention due to the orthogonality between OAM modes, which enables enhanced channel capacity. In this work, we propose and experimentally demonstrate a metasurface-based OAM mode-division multiplexing (OAM-MDM) system operating in the E-band. The system employs Fabry-Perot cavity meta-atoms that offer high transmission efficiency and precise phase control, enabling metasurfaces capable of multiplexing and demultiplexing two distinct OAM modes. We establish an electromagnetic-based effective channel model that characterizes the magnitude and phase variations between transmitted and received OAM modes from the radiated electric field. Specifically, the proposed effective wireless channel model captures not only the desired mode-to-mode transmission but also the inter-mode interference and represents these effects in a mathematically tractable form suitable for communication-theoretic analysis. Furthermore, the system performance is comprehensively evaluated by comparing the achievable rates derived from both simulations and experimental measurements under varying input power levels. Experimental results demonstrate that an achievable rate of up to 41.8 bits/s/Hz is attained at an input power of 4.9 dBm. This metasurface-based OAM-MDM system presents a promising approach for future high-capacity free-space communication.</description>
    <dc:date>2026-01-31T15:00:00Z</dc:date>
  </item>
  <item rdf:about="https://scholarworks.unist.ac.kr/handle/201301/91249">
    <title>On-Chip Direct Synthesis of 2D Semimetals for van der Waals Metal–Semiconductor Junction Transistor Arrays</title>
    <link>https://scholarworks.unist.ac.kr/handle/201301/91249</link>
    <description>Title: On-Chip Direct Synthesis of 2D Semimetals for van der Waals Metal–Semiconductor Junction Transistor Arrays
Author(s): Yang, Jihoon; Im, Jaehong; Kim, Jaemin; Lee, Hyeonwoo; Park, Jaeeun; Lee, Seungchan; Lee, Jiyeon; Kim, Byeong Kyu; Kim, Myungsoo; Yoo, Jung-Woo; Lee, Zonghoon; Kwon, Soon-Yong
Abstract: Metallic two-dimensional (2D) materials enable van der Waals (vdW) contacts that suppress metal- and defectinduced gap states via an intrinsic interlayer gap; however, their conventional integration through film transfer or high-temperature chemical vapor deposition often damages the underlying 2D semiconductors. Here, we report a low-temperature (350 °C), transferfree approach to form all-2D metal−semiconductor junctions with atomically clean vdW interfaces. A predeposited chalcogen layer (Te or Se) on 2H-MoTe2 acts as both a reactive precursor and an encapsulation layer during patterned deposition of transition metals (Mo or Pt). Upon annealing at 350 °C, the chalcogen/transition-metal stack is converted in situ into metallic 2D electrodes (1T′-MoTe2, 1T-PtTe2, or 1T-PtSe2), yielding damage-free vdW contacts. The resulting 2D transistor arrays exhibit efficient hole injection, high mobility (∼24 cm2 /V·s), low contact resistance, and ultralow Schottky barriers (∼31 meV), with device-to-device variation below 3.7%. These metrics were consistently reproduced across large-area device arrays, underscoring integration uniformity and scalability. This scalable, low-temperature integration approach enables the uniform formation of metallic 2D contacts and reliable 2D FET operation across large-area device arrays.</description>
    <dc:date>2026-02-28T15:00:00Z</dc:date>
  </item>
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