https://scholarworks.unist.ac.kr/handle/201301/101 2026-04-08T22:07:30Z 2026-04-08T22:07:30Z Hwang, Sehoon https://scholarworks.unist.ac.kr/handle/201301/91096 2026-03-26T13:16:08Z 2026-01-31T15:00:00Z

Title: A Study on the Impact of Oxygen Vacancy Engineering on the Ferroelectric Properties and Device Performance of HZO Thin Films Author(s): Hwang, Sehoon Abstract: Hafnium zirconium oxide (HZO) has emerged as a promising ferroelectric material for next- generation non-volatile memory, particularly Ferroelectric Tunnel Junctions (FTJs), due to its CMOS compatibility, strong ferroelectricity at nanometer-scale thicknesses, and suitability for three- dimensional integration. Despite these advantages, the electrical performance of HZO is highly sensitive to oxygen stoichiometry. Oxygen vacancies (Vo) can act as parasitic leakage paths, distorting polarization switching, while insufficient vacancies may limit the stabilization of the orthorhombic ferroelectric phase. Consequently, careful control of oxygen content is critical for achieving reliable, high-performance HZO-based devices. In this work, HZO thin films were systematically engineered by adjusting the H2O pulse time during Atomic Layer Deposition (ALD) to control oxygen vacancy concentration. Three sets of films—Ref HZO, +O HZO, and ++O HZO—were analyzed to understand how oxygen vacancy affects ferroelectric property and leakage behavior. The Ref HZO exhibited elevated leakage current and a rounded P–V hysteresis loop, indicating leakage-assisted polarization and reduced switching reliability. In contrast, the oxygen-rich ++O HZO displayed sharp hysteresis loops, distinct switching current peaks, and sufficiently high remnant polarization, consistent with a higher ratio of the orthorhombic phase. These results highlight the importance of an optimized oxygen vacancy concentration in stabilizing the ferroelectric phase and improving ferroelectric property. The effect of oxygen stoichiometry on device performance was further examined using FTJs. Devices based on Ref HZO showed high off current (Ioff) due to defect-mediated tunneling, which degraded the Tunneling electroresistance (TER). By contrast, ++O HZO FTJs exhibited lower Ioff and substantially improved TER, demonstrating that better stoichiometry enhances the tunneling barrier and overall switching performance. These findings also demonstrate a key trade-off in FTJs: the oxygen vacancy concentration that maximizes polarization is not necessarily optimal for TER, underscoring the need to tailor oxygen vacancy according to the specific device function. Finally, 3D Metal-Ferroelectric-Metal (MFM) devices were fabricated to probe the intrinsic ferroelectric property. P–V and I–V measurements confirmed that the trends observed in thin-film studies were preserved, demonstrating that careful vacancy engineering improves ferroelectric switching while suppressing leakage. The established link between H2O pulse time, oxygen vacancy concentration, orthorhombic phase formation, and electrical performance provides a solid foundation for optimizing both planar and 3D HZO devices. Overall, this study demonstrates that oxygen vacancy control is a key process variable for enhancing ferroelectric properties, minimizing leakage, and improving device performance. These insights offer practical guidelines for designing high performance FTJs and 3D MFM devices, while providing a material basis for next-generation ferroelectric memory applications. Major: Graduate School of Semiconductor Materials and Devices Engineering Semiconductor Materials and Devices Engineering

2026-01-31T15:00:00Z Cho, Youngseok https://scholarworks.unist.ac.kr/handle/201301/91095 2026-03-26T13:16:07Z 2026-01-31T15:00:00Z

Title: Logic Implementation Based on Selector-Only Memory for High-Efficiency In-Memory Computing Author(s): Cho, Youngseok Abstract: In-memory computing (IMC) and logic-in-memory (LIM) architectures aim to reduce data-movement overhead by enabling computation directly within memory arrays. These approaches are considered promising for improving energy efficiency and throughput in data-intensive systems. Among various device platforms, memristor-based stateful logic has been actively investigated due to its compact structure and ability to perform logic operations through resistance modulation. However, its sensitivity to device variability and the need for selectors remain major obstacles for efficient logic implementation. In this work, we present a stateful logic scheme based on Selector-Only Memory (SOM), which operates through threshold switching rather than controlled resistance tuning. The polarity-dependent variation of threshold voltage in SOM devices enables digital-like state transitions and provides a stable mechanism for realizing logic implications, the resulting switching outcomes are represented by distinct threshold-defined states. Fundamental IMP and RNIMP functions were experimentally validated, and these primitives were sequentially combined to implement higher-order Boolean logic. The device-level threshold distributions, cycle-to-cycle stability, and drift characteristics were experimentally analyzed to identify operating margins that ensure reliable logic behavior. To evaluate the impact of variability on logic accuracy, Monte Carlo simulations were performed using experimentally extracted threshold voltage statistics. The results show that logic errors primarily originate from threshold variation, external-resistor selection, and drift-induced boundary shifts. Despite these sources of variation, SOM-based logic maintains stable performance within an optimized operating window defined by high- and low-voltage-state and appropriate pulse conditions. Overall, this study demonstrates that SOM provides a compact and reliable platform for threshold-driven logic-in-memory operation, with logic operations governed solely by threshold voltage. The combination of experimental verification and error simulations establishes SOM as a feasible device structure for efficient logic-in-memory architectures. Major: Graduate School of Semiconductor Materials and Devices Engineering Semiconductor Materials and Devices Engineering

2026-01-31T15:00:00Z Jeong, JaeYoon https://scholarworks.unist.ac.kr/handle/201301/91094 2026-03-26T13:16:05Z 2026-01-31T15:00:00Z

Title: Performance Enhancement of Oxide-Based Source-Gated Transistors via Structural and Contact Engineering Author(s): Jeong, JaeYoon Abstract: A 2T1C driving transistor (TFT), which is commonly used in OLED pixels, must supply a constant current to the OLED. However, as the operating time of the device increases, the drain voltage (Vd) may vary, leading to corresponding variations in the drain current. To ensure a stable current supply, the transistor must have a low saturation voltage and strong current saturation characteristics. In this study, a top-gate SGT structure that exhibits these characteristics was fabricated and its electrical properties were characterized. Furthermore, to address the relatively low drain current associated with SGTs due to the source barrier, process and structural optimizations were implemented by increasing the source– gate overlap and modifying the drain electrode metal. Consequently, a linear increase in drain current was observed as the source–gate overlap increased, and replacing the drain electrode from Pt to Au improved the drain current by more than one order of magnitude. Major: Graduate School of Semiconductor Materials and Devices Engineering Semiconductor Materials and Devices Engineering

2026-01-31T15:00:00Z Im, Jaehong https://scholarworks.unist.ac.kr/handle/201301/91093 2026-03-26T13:16:04Z 2026-01-31T15:00:00Z

Title: Transfer-free Fabrication of All-2D Metal-Semiconductor Junctions for High-Performance 2D Electronics Author(s): Im, Jaehong Abstract: Modern electronics have advanced by continuous down-scaling over the past decades, leading to high integration density and remarkable improvements in speed, efficiency, and functionality. However, conventional bulk semiconductor devices are approaching their quantum limits due to severe short-channel effects (SCEs) and surface scattering, posing a major bottleneck for further scaling. These challenges underscore the urgent need for alternative materials, prompting the development of semiconducting two-dimensional (2D) transition metal dichalcogenides (TMDs) as channels for field-effect transistors (FETs). With atomically thin layered structure and dangling bond-free surfaces, 2D TMDs offer strong electrostatic control and superior carrier transport, enabling reliable operation even at the atomic scale. Nevertheless, establishing high-quality metal contacts on surface 2D TMDs remains a critical challenge owing to their ultrathin body and delicate lattices. Van der Waals (vdW) contacts, particularly using 2D semimetals leverage the intrinsic vdW gap to form atomically sharp metal–semiconductor junctions (MSJs) while preserving the structural integrity of the 2D channel. However, the fabrication of 2D semimetals often relies on transfer-based approaches to avoid fabrication-induced damage, including metal atom bombardment during precursor deposition and thermal damage from high-temperature chemical vapor deposition (CVD, >500 °C). These processes can induce interfacial defects in the underlying 2D channel, ultimately degrading device performance and reliability. In this thesis, we report a low-temperature (350 °C) synthesis method of 2D semimetals and transfer-free fabrication into all-2D MSJ with clean interfaces. First, by employing all-solid-state chalcogen/transition metal stacks (CTS; Te/Mo, Te/Pt, and Se/Pt), we synthesized diverse 2D semimetals, including 1T′-MoTe₂, 1T-PtTe₂, and 1T-PtSe₂ upon annealing at 350 °C (Chapter 2). We investigated the conversion of CTS into 2D semimetals using Raman spectroscopy and XPS analysis. Furthermore, the CTS-synthesized 2D semimetals show wafer-scale compatibility and appropriate electrical properties, including sheet resistance (RSH) and work function. To investigate the clean MSJ enabled by the CTS approach, we fabricated 2H-MoTe₂ devices in which CTS-synthesized 2D semimetals served as source and drain electrodes (Chapter 3). Te/Mo CTS stacks were deposited on 2H-MoTe₂ and converted into 1T′-MoTe₂ through annealing at 350 °C. In this process, the Te layer acts simultaneously as an encapsulation layer and chalcogen precursor, effectively protecting the underlying 2H-MoTe₂ surface during fabrication process and enabling the formation of clean 2D/2D heterojunctions. The protective effect was further validated by comparing bare 2H-MoTe₂ with 2H-MoTe₂/Te heterostructures, and cross-sectional TEM analysis confirmed the formation of atomically sharp interfaces and clean all-2D MSJs after annealing. In addition, first-principles calculations indicate that Te and Se atoms can migrate toward Te vacancies in the underlying 2H-MoTe2 through relatively low energy barriers (Eb ≈ 0.42–0.56 eV), suggesting a mild chalcogen-healing effect that further contributes to interface preservation. The final section explores the electrical characteristics of CTS-driven all-2D MSJ FET arrays (Chapter 4). We integrated diverse CTS-synthesized 2D semimetals, including 1T′-MoTe₂, 1T-PtTe₂, and 1T-PtSe₂, to form all-2D MSJ heterojunctions compatible with the 2H-MoTe₂ channel. The resulting devices exhibit outstanding electrical performance, including efficient charge injection, high field-effect hole mobility (μₕ ≈ 24 cm²/V·s) with low device-to-device variation (3.7%), and ideal Schottky barrier heights, with the lowest value of 31 meV achieved for the 1T′/2H-MoTe₂ MSJ. Other CTS-derived 2D electrodes likewise showed favorable band alignment and comparable electrical properties, demonstrating the generality and robustness of the CTS integration strategy. Collectively, these results establish CTS as a scalable, CMOS-compatible method for realizing high-performance 2D metallic contacts. Major: Graduate School of Semiconductor Materials and Devices Engineering Semiconductor Materials and Devices Engineering

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