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A Design Framework for Cost-Efficient Sorters With Arbitrary Input/Output Constraints File

Kim, Jaehee , Han, Sangil , Kam, Dongyun , Kong, Byeong Yong , Lee, Youngjoo

Article Issue Date2024-12 View21
Ambassy: A Runtime Framework to Delegate Trusted Applications in an ARM/FPGA Hybrid System File

Hwang, Dongil , Yeleuov, Sanzhar , Seo, Jiwon , Chung, Minu , Moon, Hyungon , Paek, Yunheung

Article Issue Date2023-02 View139
Double MAC on a DSP: Boosting the Performance of Convolutional Neural Networks on FPGAs File

Lee, Sugil , Kim, Daewoo , Nguyen, Dong , Lee, Jongeun

Article Issue Date2019-05 View143
Hotness- and Lifetime-Aware Data Placement and Migration for High-Performance Deep Learning on Heterogeneous Memory Systems File

Han, Myeonggyun , Hyun, Jihoon , Park, Seongbeom , Baek, Woongki

Article Issue Date2020-03 View125
Low-Latency SCL Polar Decoder Architecture Using Overlapped Pruning Operations File

Kam, Dongyun , Kong, Byeong Yong , Lee, Youngjoo

Article Issue Date2023-03 View24
Partial Sum Quantization for Reducing ADC Size in ReRAM-based Neural Network Accelerators File

Azamat, Azat , Asim, Faaiz , Kim, Jintae , Lee, Jongeun

Article Issue Date2023-12 View145
SDRP: Safe, Efficient, and SLO-Aware Workload Consolidation through Secure and Dynamic Resource Partitioning File

Han, Myeonggyun , Baek, Woongki

Article Issue Date2022-07 View119
The Development of Silicon for AI: Different Design Approaches File

Lee, Kyuho Jason , Lee, Jinmook , Choi, Sungpill , Yoo, Hoi-Jun

Article Issue Date2020-12 View153
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