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Showing results 1 to 2 of 2

Issue DateTitleAuthor(s)TypeView
2016-07Synthesis of dual-mode circuits through library design, gate sizing, and clock-tree optimizationKim, Sangmin; Kang, Seokhyeong; Shin, YoungsooARTICLE493
2016-03Wakeup scheduling and its buffered tree synthesis for power gating circuitsKim, Sangmin; Paik, Seungwhun; Kang, Seokhyeong; Shin, YoungsooARTICLE536
Showing results 1 to 2 of 2

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