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Impact of BTBT, stress and interface charge on optimum Ge in SiGe pMOS for low power applications File

Dhar, S. , Noh, H.K. , Kim, S.J. , Kim, H.W. , Wu, Z. , Lee, W.S. , Bhuwalka, K.K. , Kim, J.C. , Jeong, Changwook , Kwon, U.H. , et al

Conference Paper Issue Date2016-10-20 View72
Si FinFET based 10nm technology with multi Vt gate stack for low power and high performance applications File

Cho, H.-J. , Oh, H.S. , Nam, K.J. , Kim, Y.H. , Yeo, K.H. , Kim, W.D. , Chung, Y.S. , Nam, Y.S. , Kim, S.M. , Kwon, W.H. , et al

Conference Paper Issue Date2016-06-13 View98
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