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Showing results 1 to 17 of 17

A Systematic Removal of Minimum Implant Area Violations under Timing Constraint

Jeong, Eunsol , Park , Heechun , Kim, Taewhan

Conference Paper Issue Date2022-03-14 View91
Allocation of Always-On State Retention Storage for Power Gated Circuits-Steady-State- Driven Approach File

Kim, Taewhan , Park , Heechun

Article Issue Date2021-03 View105
Challenges on DTCO Methodology Towards Deep Submicron Interconnect Technology

Park , Heechun , Chang, Kyungjoon , Kim, Taewhan

Conference Paper Issue Date2021-10-06 View66
Clock TSV Fault-Tolerant 한 3 차원 IC 설계를 위한 TSV 공유 알고리즘

Park, Heechun , Kim, Taewhan

Conference Paper Issue Date2012-06-27 View71
Comprehensive Technique for Designing and Synthesizing TSV Fault-Tolerant 3D Clock Trees File

Park, Heechun , Kim, Taewhan

Conference Paper Issue Date2013-11-18 View58
DTOC-P: Deep-Learning-Driven Timing Optimization Using Commercial EDA Tool With Practicality Enhancement File

Ahn, Jaehoon , Chang, Kyungjoon , Choi, Kyu-Myung , Kim, Taewhan , Park, Heechun

Article Issue Date2024-08 View92
DTOC: integrating Deep-learning driven Timing Optimization into the state-of-the-art Commercial EDA tool

Chang, Kyungjoon , Park, Heechun , Kim, Taewhan

Conference Paper Issue Date2023-04-17 View70
Eliminating Minimum Implant Area Violations With Design Quality Preservation File

Jeong, Eunsol , Kim, Taewhan , Park , Heechun

Article Issue Date2023-05 View96
Fault Coverage and Resource Analysis for Diverse Structures of Clock TSV Fault-Tolerant Units in 3D ICs

Park, Heechun , Kim, Taewhan

Conference Paper Issue Date2013-11-17 View50
Hybrid asynchronous circuit generation amenable to conventional EDA flow File

Park , Heechun , Kim, Taewhan

Article Issue Date2019-01 View81
Minimum Implant Area-Aware Threshold Voltage Refinement in Pre-Placement

Jeong, Eunsol , Park, Heechun , Kim, Taewhan

Conference Paper Issue Date2021-08-09 View58
Size-dependent antibiotic effect of graphene oxide

Kim, Ungsoo , Park, Kwang Hyun , Lee, Junghyun , Kim, Taewhan , Kwon, Heeyun , Mitchell, Robert J. , Yang, Changduk , Park, Hyesung

Conference Paper Issue Date2017-04-06 View78
Speeding-up neuromorphic computation for neural networks: Structure optimization approach File

Park , Heechun , Kim, Taewhan

Article Issue Date2022-01 View92
Structure Optimizations of Neuromorphic Computing Architectures for Deep Neural Networks

Park, Heechun , Kim, Taewhan

Conference Paper Issue Date2018-03-19 View60
Synthesis of TSV Fault-Tolerant 3-D Clock Trees File

Park, Heechun , Kim, Taewhan

Article Issue Date2015-02 View89
Synthesizing Asynchronous Circuits Toward Practical Use File

Park, Heechun , Kim, Taewhan

Conference Paper Issue Date2016-07-11 View76
비동기식 회로 설계 구조에 대한 전력 및 면적 비교

Park, Heechun , Kim, Taewhan

Conference Paper Issue Date2015-11-27 View61
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