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Showing results 1 to 3 of 3

Issue DateTitleAuthor(s)TypeView
2018-02An Optimal Gate Design for the Synthesis of Ternary Logic CircuitsKang, Seokhyeong; Kim, SunmeanMaster's thesis280
2018-10Ternary full adder using multi-threshold voltage graphene barristorsHeo, Sunwoo; Kim, Sunmean; Kim, Kiyung; Lee, Hyeji; Kim, So-Young; Kim, Yun Ji; Kim, Seong Mo; Lee, Ho-In; Lee, Segi; Kim, Kyung Rok; Kang, Seokhyeong; Lee, Byoung HunARTICLE1083
2019-07Tunnelling-based ternary metal–oxide–semiconductor technologyJeong, Jae Won; Choi, Young Eun; Kim, Woo Seok; Park, Jee-Ho; Kim, Sunmean; Shin, Sunhae; Lee, Kyuho; Chang, Jiwon; Kim, Seong-Jin; Kim, Kyung RokARTICLE666
Showing results 1 to 3 of 3