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Showing results 1 to 9 of 9

Issue DateTitleAuthor(s)TypeView
2020-09A Logic Synthesis Methodology for Low-Power Ternary Logic CircuitsKim, Sunmean; Lee, Sung-Yun; Park, Sunghye; Kim, Kyung Rok; Kang, SeokhyeongARTICLE65
2021-02A New Design Methodology for Ternary Circuits and SystemsKim, Kyung Rok; Kim, SunmeanDoctoral thesis38
2016-10-26A novel design methodology for error-resilient circuits in near-Threshold computingLee, Jaemin; Kim, Sunmean; Kim, Youngmin; Kang, SeokhyeongCONFERENCE137
2018-01-22An optimal gate design for the synthesis of ternary logic circuitsKim, Sunmean; Lim, Taeho; Kang, SeokhyeongCONFERENCE46
2018-02An Optimal Gate Design for the Synthesis of Ternary Logic CircuitsKang, Seokhyeong; Kim, SunmeanMaster's thesis364
2019-05-21Design of Quad-Edge-Triggered Sequential Logic Circuits for Ternary LogicKim, Sunmean; Lee, Sung-Yun; Park, Sunghye; Kang, SeokhyeongCONFERENCE45
2018-10Ternary full adder using multi-threshold voltage graphene barristorsHeo, Sunwoo; Kim, Sunmean; Kim, Kiyung; Lee, Hyeji; Kim, So-Young; Kim, Yun Ji; Kim, Seong Mo; Lee, Ho-In; Lee, Segi; Kim, Kyung Rok; Kang, Seokhyeong; Lee, Byoung HunARTICLE1372
2019-05-21Ternary Logic Synthesis with Modified Quine-McCluskey AlgorithmLee, Sung-Yun; Kim, Sunmean; Kang, SeokhyeongCONFERENCE49
2019-07Tunnelling-based ternary metal–oxide–semiconductor technologyJeong, Jae Won; Choi, Young Eun; Kim, Woo Seok; Park, Jee-Ho; Kim, Sunmean; Shin, Sunhae; Lee, Kyuho; Chang, Jiwon; Kim, Seong-Jin; Kim, Kyung RokARTICLE1176
Showing results 1 to 9 of 9

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