| 2017-09-09 | Advanced non-quasi-static(NQS) compact model for characterization of non-resonant plasmonic terahertz detector | Ahn, Sang Hyo; Ryu, Min Woo; Jang, Esan; Jeon, Hyeong Ju; Kim, Kyung Rok | CONFERENCE | 56 |
| 2018-02-05 | Analysis of Silicon MOSFET-based Plasmonic Terahertz Detection Delay with Advanced Non-Quasi-Static Compact Model | Ah, Sang Hyo; Ryu, Min Woo; Jang, Esan; Jeon, Hyeong Ju; Kim, Kyung Rok | CONFERENCE | 37 |
| 2017-05-22 | CMOS-Compatible Ternary Device Platform for Physical Synthesis of Multi-valued Logic Circuits | Shin, Sunhae; Jang, Esan; Jeong, Jae Won; Kim, Kyung Rok | CONFERENCE | 47 |
| 2018-02-05 | Common Body for Ternary CMOS Logic Gates for Endurance of the Input Pattern Effects on Intermediate State Level | Jang, Esan; Shin, Sunhae; Jeong, Jae Won; Kim, Kyung Rok | CONFERENCE | 41 |
| 2015-08 | Compact Design of Low Power Standard Ternary Inverter Based on OFF-State Current Mechanism Using Nano-CMOS Technology | Shin, Sunhae; Jang, Esan; Jeong, Jae Won; Park, Byung-Gook; Kim, Kyung Rok | ARTICLE | 848 |
| 2017-02-15 | Compact Model for Positive Gain-Embedded Voltage Transfer Curve of Inverter Based on Novel I-V Curves for Multi-Peak NDR | Jeong, Jaewon; Shin, Sunhae; Jang, Esan; Kim, Kyung Rok | CONFERENCE | 27 |
| 2017-02-14 | Demonstration of CMOS with Gate-Bias Independent Junction Band-to-Band Tunneling Current for Standard Ternary Inverter | Sunhae Shin; Jang, Esan; Jeong, Jae Won; Kim, Kyung Rok | CONFERENCE | 29 |
| 2016-06-12 | Demonstration of standrad ternary inverter based on CMOS technology | Shin, Sunhae; Jang, Esan; Jeong, Jae Won; Kim, Kyung Rok | CONFERENCE | 57 |
| 2018-02-05 | Design of THz Aperture based on Near-Field Microscopy Technology for High Resolution THz Imaging | Jeon, Hyeong Ju; Ryu, Min Woo; Jang, Esan; Ahn, Sang Hyo; Kim, Kyung Rok | CONFERENCE | 28 |
| 2016-06-12 | Device optimization on gate oxide and spacer dielectric permittivity for 'well-tempered' nanoscale MOSFET | Jang, Esan; Shin, Sunhae; Jung, Jae Won; Jung, Yu Jung; Kim, Kyung Rok | CONFERENCE | 31 |
| 2015-06 | Gate induced drain leakage reduction with analysis of gate fringing field effect on high-kappa/metal gate CMOS technology | Jang, Esan; Shin, Sunhae; Jung, Jae Won; Kim, Kyung Rok | ARTICLE | 729 |
| 2018-06 | Low Leakage III-V/Ge CMOS FinFET Design for High-Performance Logic Applications with High-kappa Spacer Technology | Jang, Esan; Shin, Sunhae; Jeong, Jae Won; Kim, Kyung Rok | ARTICLE | 341 |
| 2015-07-02 | Multi-Valued Logic Based on CMOS technology | Kim, Kyung Rok; Shin, Sunhae; Jang, Esan; Jung, Jae Won | CONFERENCE | 33 |
| 2014-06-08 | Standard Ternary Inverter Based on Junction Leakage-Enhanced Nanoscale Planar CMOS and Its Variation Immunity | Kim, Kyung Rok; Shin, Sunhae; Jang, Esan | CONFERENCE | 32 |
| 2016-02-23 | Tunnel FET-based negative differential resistance device with triple-peaks and ultra-high peak-to-valley current ratio | Jae Won Jeong; Shin, Sunhae; Jang, Esan; Kim, Kyung Rok | CONFERENCE | 29 |
| 2017-07-26 | Ultra-Low Standby Power and Static Noise-Immune Standard Ternary Inverter Based on Nanoscale Ternary CMOS Technology | Shin, Sunhae; Jeong, Jae Won; Jang, Esan; Kim, Kyung Rok | CONFERENCE | 112 |
