Real hardware-based RRAM error compensation and characterization for deep learning acceleration

Abstract

RRAM Crossbar Arrays (RCAs) have the potential to enable extremely fast and efficient matrix-vector multiplication (MVM), a pivotal operation in various applications. In particular, passive (i.e., 0T1R) RCAs do not take any silicon area, thus simplifying design and minimizing cost as well as providing better scalability. However, ensuring correct operation on passive RCAs is much more challenging than with active RCAs due to programming challenges and resultant variations, which has been difficult to study due to the lack of adequate simulation models. In this paper we use real RRAM hardware to ex- amine the RCA programming and variability issue. We find that even small offset in DACs can cause significant error in MVM result, which we term MVM error problem. We also propose two methods to address the MVM error problem. Our experimental results using real RRAM hardware and digital interface hardware demonstrate that our proposed methods exhibit substantial enhancements, achieving a 74.68% increase in R2 score and an 85.2% reduction in RMSE compared to the previous work. We fur- ther perform network-level accuracy evaluation. In terms of top-1 accuracy, our approach outperforms previous work by 57.82% in the convolutional neural network and by 84.36% in the multi-layer percep- tron, respectively. Through our macro-level variability characterization, we obtain matched variability parameters between our model and the output obtained from programming real hardware in a specific variability condition. With the parameter, we achieve a Structural Similarity Index Measure (SSIM) result of 0.996.