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DC Field | Value | Language |
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dc.citation.endPage | 2437 | - |
dc.citation.number | 11 | - |
dc.citation.startPage | 2424 | - |
dc.citation.title | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS | - |
dc.citation.volume | 28 | - |
dc.contributor.author | Kim, Jinwoo | - |
dc.contributor.author | Murali, Gauthaman | - |
dc.contributor.author | Park, Heechun | - |
dc.contributor.author | Qin, Eric | - |
dc.contributor.author | Kwon, Hyoukjun | - |
dc.contributor.author | Chekuri, Venkata Chaitanya Krishna | - |
dc.contributor.author | Rahman, Nael Mizanur | - |
dc.contributor.author | Dasari, Nihar | - |
dc.contributor.author | Singh, Arvind | - |
dc.contributor.author | Lee, Minah | - |
dc.contributor.author | Torun, Hakki Mert | - |
dc.contributor.author | Roy, Kallol | - |
dc.contributor.author | Swaminathan, Madhavan | - |
dc.contributor.author | Mukhopadhyay, Saibal | - |
dc.contributor.author | Krishna, Tushar | - |
dc.contributor.author | Lim, Sung Kyu | - |
dc.date.accessioned | 2024-03-13T16:05:09Z | - |
dc.date.available | 2024-03-13T16:05:09Z | - |
dc.date.created | 2024-03-13 | - |
dc.date.issued | 2020-11 | - |
dc.description.abstract | A new trend in system-on-chip (SoC) design is chiplet-based IP reuse using 2.5-D integration. Complete electronic systems can be created through the integration of chiplets on an interposer, rather than through a monolithic flow. This approach expands access to a large catalog of off-the-shelf intellectual properties (IPs), allows reuse of them, and enables heterogeneous integration of blocks in different technologies. In this article, we present a highly integrated design flow that encompasses architecture, circuit, and package to build and simulate heterogeneous 2.5-D designs. Our target design is 64core architecture based on Reduced Instruction Set Computer (RISC)-V processor. We first chipletize each IP by adding logical protocol translators and physical interface modules. We convert a given register transfer level (RTL) for 64-core processor into chiplets, which are enhanced with our centralized network-onchip. Next, we use our tool to obtain physical layouts, which is subsequently used to synthesize chip-to-chip I/O drivers and these chiplets are placed/routed on a silicon interposer. Our package models are used to calculate power, performance, and area (PPA) and reliability of 2.5-D design. Our design space exploration (DSE) study shows that 2.5-D integration incurs 1.29x power and 2.19x area overheads compared with 2-D counterpart. Moreover, we perform DSE studies for power delivery scheme and interposer technology to investigate the tradeoffs in 2.5-D integrated chip (IC) designs. | - |
dc.identifier.bibliographicCitation | IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, v.28, no.11, pp.2424 - 2437 | - |
dc.identifier.doi | 10.1109/TVLSI.2020.3015494 | - |
dc.identifier.issn | 1063-8210 | - |
dc.identifier.scopusid | 2-s2.0-85094871158 | - |
dc.identifier.uri | https://scholarworks.unist.ac.kr/handle/201301/81627 | - |
dc.identifier.wosid | 000584745800016 | - |
dc.language | 영어 | - |
dc.publisher | IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC | - |
dc.title | Architecture, Chip, and Package Codesign Flow for Interposer-Based 2.5-D Chiplet Integration Enabling Heterogeneous IP Reuse | - |
dc.type | Article | - |
dc.description.isOpenAccess | FALSE | - |
dc.relation.journalWebOfScienceCategory | Computer Science, Hardware & Architecture; Engineering, Electrical & Electronic | - |
dc.relation.journalResearchArea | Computer Science; Engineering | - |
dc.type.docType | Article | - |
dc.description.journalRegisteredClass | scie | - |
dc.description.journalRegisteredClass | scopus | - |
dc.subject.keywordAuthor | 2.5-D integrated chip (IC) | - |
dc.subject.keywordAuthor | chiplet | - |
dc.subject.keywordAuthor | electronic design automation (EDA) flow | - |
dc.subject.keywordAuthor | interposer | - |
dc.subject.keywordAuthor | power | - |
dc.subject.keywordAuthor | performance | - |
dc.subject.keywordAuthor | and area (PPA) | - |
dc.subject.keywordAuthor | reliability | - |
dc.subject.keywordPlus | CIRCUITS | - |
dc.subject.keywordPlus | ICS | - |
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