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A 320μV-Output Ripple and 90ns-Settling Time at 0.5V Supply Digital-Analog-Hybrid LDO Using Multi-Level Gate-Voltage Generator and Fast-Decision PD Detector
- Author(s)
- Lim, Younghyun, Lee, Jeonghyun, Lee, Yongsun, Yoo, Seyeon, Choi, Jaehyouk
- Issued Date
- 2018-09-03
- Citation
- 44th IEEE European Solid State Circuits Conference, ESSCIRC 2018, pp.94 - 97
- Abstract
- This work presents a digital-analog-hybrid LDO (HLDO) using a multi-level gate-voltage generator (MGG) to achieve a small output ripple (VR) and a fast-transient response. Using the MGG that can partially turn on transistors in the power MOSFET (Mp) and thus reduce Mp's LSB current, VR was limited to less than 320 μV. Also, a fast-decision PD detector having a non-zero decision level expedited the switching of transistors in Mp, thereby reducing the settling time to less than 90 ns.
- Publisher
- IEEE
- ISBN
- 978-153865404-0
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