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김성진

Kim, Seong-Jin
Bio-inspired Advanced Sensors Lab.
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dc.citation.conferencePlace KO -
dc.citation.conferencePlace Hotel Inter-Burgo DaeguDaegu -
dc.citation.endPage 69 -
dc.citation.startPage 68 -
dc.citation.title International SoC Design Conference -
dc.contributor.author Lee, Taeju -
dc.contributor.author Cha, Ji-Hyoung -
dc.contributor.author Han, Su-Hyun -
dc.contributor.author Kim, Seong-Jin -
dc.contributor.author Je, Minkyu -
dc.date.accessioned 2024-02-01T01:06:29Z -
dc.date.available 2024-02-01T01:06:29Z -
dc.date.created 2018-12-20 -
dc.date.issued 2018-11-13 -
dc.description.abstract This paper presents a fully differential multi-channel neural recording system. The system consists of four key blocks which are a low-noise amplifier (LNA), programmable gain amplifier (PGA), buffer, and successive approximation register ADC (SAR ADC). The input stage of the OTA used in LNA is designed as the inverter-based structure for improving the current efficiency. For an energy efficient system, the dual sample-and-hold (S/H) structure is applied to the SAR ADC. Each channel consumes the power of 4.86 W/Channel and
achieves an input-referred noise of 2.58 Vrms. The implemented IC operates under a 1-V supply voltage for core blocks and 1.8-V for output digital buffers. The system is implemented in a standard 1P6M 0.18-m CMOS process.
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dc.identifier.bibliographicCitation International SoC Design Conference, pp.68 - 69 -
dc.identifier.doi 10.1109/ISOCC.2018.8649952 -
dc.identifier.scopusid 2-s2.0-85063191290 -
dc.identifier.uri https://scholarworks.unist.ac.kr/handle/201301/80455 -
dc.identifier.url https://ieeexplore.ieee.org/document/8649952 -
dc.language 영어 -
dc.publisher Institute of Electrical and Electronics Engineers Inc. -
dc.title A 4.86 μW/Channel Fully Differential Multi-Channel Neural Recording System -
dc.type Conference Paper -
dc.date.conferenceDate 2018-11-12 -

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