dc.citation.conferencePlace |
CN |
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dc.citation.conferencePlace |
Fredericton |
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dc.citation.endPage |
163 |
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dc.citation.startPage |
158 |
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dc.citation.title |
49th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2019 |
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dc.contributor.author |
Lee, Sung-Yun |
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dc.contributor.author |
Kim, Sunmean |
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dc.contributor.author |
Kang, Seokhyeong |
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dc.date.accessioned |
2024-02-01T00:10:54Z |
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dc.date.available |
2024-02-01T00:10:54Z |
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dc.date.created |
2019-08-14 |
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dc.date.issued |
2019-05-21 |
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dc.description.abstract |
Logic synthesis has been increasingly important to accelerate the development of high-level systems. However, in multi-valued logic, logic synthesis methods that can process emerging devices are deficient. We propose and automate a method to synthesize ternary logic circuits. Our design of ternary logic circuits is based on static gate design, and exploits carbon nanotube field-effect transistors. We optimize ternary logic circuits by minimizing the number of transistors with a modified Quine-McCluskey algorithm. Our proposed method has improved power-delay product by 52.72 % over the state-of-the-art method for a ternary half adder, and by 68.06 % for a ternary multiplier. We also have improved power-delay product by 37.30 % over the state-of-the-art method for a ternary full adder that has high load capacitance. Our design has an average of 42.43 % fewer transistors than the existing design for circuits that have large number of inputs. As circuits become larger, the improved power-delay product and reduced transistor count are advantageous. |
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dc.identifier.bibliographicCitation |
49th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2019, pp.158 - 163 |
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dc.identifier.doi |
10.1109/ISMVL.2019.00035 |
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dc.identifier.issn |
0195-623X |
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dc.identifier.scopusid |
2-s2.0-85069205250 |
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dc.identifier.uri |
https://scholarworks.unist.ac.kr/handle/201301/79780 |
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dc.identifier.url |
https://ieeexplore.ieee.org/document/8758768 |
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dc.language |
영어 |
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dc.publisher |
IEEE Computer Society |
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dc.title |
Ternary Logic Synthesis with Modified Quine-McCluskey Algorithm |
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dc.type |
Conference Paper |
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dc.date.conferenceDate |
2019-05-21 |
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